The theoretical memory limits in 16, 32 and 64 bit machines are as follows ...
The fundamental flaw here is the notion that the "bit width" of the processor, which is usually the size of the machine's general-purpose registers, is necessarily the same as the width of RAM addresses.
In x86 with paging enabled, but without PAE, the addresses that program and OS code use are called "linear addresses" by Intel - we usually call them "virtual addresses". They're 32 bits wide. This permits a 4 GiB virtual address space.
But it is more or less coincidence, merely an artifact of the format of page table entries that the size of a physical (RAM) address is also 32 bits.
With PAE the latter is 36 bits (at first... wider in later implementations). So, just because it is, for example, a "32 bit machine" does not mean that physical memory addresses are limited to 32 bits.
The industry has a long history of machines whose "bit width" did not match their maximum physical address size. For example, the VAX architecture defines a 32-bit machine, and virtual addresses (which are the addresses used by code once address translation is turned on) are indeed 32 bits wide... but the VAX's physical addresses are only 30 bits wide - and half of the physical address space is devoted to I/O device registers, so maximum RAM was only 512 MiB.
Even without address translation hardware, it is not necessarily the case that the machine's "bit width" defines the maximum RAM address. Example: The CDC "upper 3000" series were 36-bit machines. Do you think they could address 64 GiB of RAM? Not hardly! Those machines came out in the mid-60s! Heck, we couldn't even have 64 GB of disk space in those days. (The CDC 6000 series were 60-bit machines. Need I go on?)