(Below is a conceptual explanation in almost plain words.)
Each device has some resource. Someone needs to access that resource. This someone can be cpu or other devices.
CPU requests resources from the outside world by sending out addresses. These addresses are usually classified into different categories. Such as memory address or IO address. Different categories are called different address spaces, which implies different instructions.
Memory addresses work with load-store instructions such as mov
. IO addresses with IO instructions such as in
or out
. Different flavors of CPU use different categorization schemas. Some companies prefer to use memory addresses to address everything, such as some Motorola CPUs. Some companies prefer to use separate memory and IO addresses, such as Intel. There's a saying that programmers like Motorola because they only need to care about load-store instructions. But electrical engineers like Intel because the separation of memory/IO addresses simplifies the hardware implementation.
Anyway, after addresses are put on the address bus, some device should respond to that address by placing data on the data bus. The hardware pieces are all connected together somehow. There's many switch/decoders along the way. With different addresses, different requests are routed to different places. Kind of like a network.
Each device in the system must know which requests it should respond. The devices tell this through address-mapping, i.e. a device remembers which addresses it should respond. And this usually comes in the form an address range.
Someone must tell a device such info. And that someone can be OS/BIOS/firmware. When they do this arrangement, they are doing the address-mapping.
For PCI/PCIe, we need to program the BAR decoder/register of the device to tell it the base address of the addresses arriving at it. And the PCIe device implicitly/inherently knows the address range size used by each BAR. And OS/FW/BIOS can know that by writing all 1s to the BAR register. With this base/size info, the PCIe device can accurately identify which BAR an arriving address falls into. And then properly calculate the offset from the arriving address. And finally access the RAM/registers implemented on the PCIe device.