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For an example, I put just output from 1 core of a 16 core machine.

What does the output mean by "cpuid level" of "6"? Also, what do "bogomips" of "5992.10" and "clflush size" of "64" mean?

processor    :    0
vendor_id    :    GenuineIntel
cpu family   :    15
model        :    6
model name   :    Intel(R) Xeon(TM) CPU 3.00GHz
stepping     :    8
cpu MHz      :    2992.689
cache size   :    4096 KB
physical id  :    0
siblings     :    4
core id      :    0
cpu cores    :    2
fpu          :    yes
fpu_exception:    yes
cpuid level  :    6
wp           :    yes
flags        :    fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge 
                  mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 
                  ss ht tm syscall nx lm constant_tsc pni monitor ds_cpl 
                  vmx cid cx16 xtpr lahf_lm
bogomips     :    5992.10
clflush size :    64
cache_alignment:  128
address sizes:    40 bits physical, 48 bits virtual
power management:
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2 Answers 2

most of the information that is displayed is obtained from the x86 instruction 'cpuid'. The 'level' is the maximum option set that you can safely use to interrogate the processor for information.

The Intel app note at http://www.intel.com/assets/pdf/appnote/241618.pdf contains a lot of detail on the instruction. I believe the 'level' equates to the 'function' that is listed in the document.

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bogomips is s based on the speed of a very specific set of instructions in a loop, the kernel uses the value for some timing loops. It is pretty much meaningless outside this context - some incorrectly think that it is a measure of CPU speed (which it is in this one very specific context, but not generally).

clfush in the features list refers to the availability of the cache-line flushing feature, an instruction to tell the CPU's cache that a particular block of data is no longer needed or perhaps no longer valid (so should be re-read from elsewhere if needed). I'm guessing that the size specified in clflush size would be the granularity with which this process can be controlled - i.e. the smallest block that can be flushed (probably related directly to the line width of the CPU's L1 caches). This too is probably not a useful thing to know, unless you are a CPU engineer or otherwise trying to debug something at a very very low level.

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