I have just a simple question. Today memory DDR chips are 64 bits wide, and the CPU data bus is also 64 bits wide. But memory is stil organised in single bytes. So, what I want to ask is, when CPU selects some memory adress, it should be one byte, right? Becouse the lowest memory portion you can access is 1 byte. But, if you get 1 byte per 1 adress, why is memory bus 8 bytes wide?
We refer to our computer architectures as
In fact even as you use a Intel based byte-address computer, the memory you use is usually accessed with a different width (64 bit as in your example).
This helps in addressing larger amount of data with lesser address space.
My answer actually completes here, however, I ramble further to talk about how memory accesses are done which might help think about the abstractions implemented (and maybe also motivate you to read up some more on memories).
If you have seen a DDR-RAM stick, you would recall seeing several chips on a green PCB. These are striped together for a parallel access. That makes your RAM accesses faster.
In front of the RAM module is a Memory Controller. This is designed to access data in a wider bit-width (32, 64, 128 bits -- depending on the design).
When you access a byte from this memory space, the memory controller actually gets a complete "memory word"; here, a word is actually the width of this access from the memory controller.
Which means if its 128 bit width, you always fetch 16 bytes from addresses which are multiples of 16.
So, now what happens when you want a byte at address 18 (= 16+2)?
More interestingly, what happens when you want to write a byte at address 19?
All this is quite an effort. The memory controller is designed to manage this and infact works on multiple requests in parallel.
We are not even talking about 'dual-channel' yet
Here is a reference from Wikipedia on DDR SDRAM organization
From the Memory Controller page
It's faster to transfer large amounts of data 8 bytes at a time instead of 1. Besides, there's no way to actually address single bytes outside of CPU cache anyways since the last few address bits don't have physical connections anymore (because they're not needed).
I speak with no great expertise but roughly...
Processors retrieve one word at a time (i.e. a 64 bit processor retrieves 8 bytes at a time). However when retrieving a single byte they effectively throw away the other 7 bytes. The memory addressing scheme is still usually thought of as bytes, but if you are pulling data as fast as possible you use word aligned addresses, that is addresses that are divisible by the word length in bytes. In a 64 bit system you'll use addresses 0, 8, 16, 24, etc.
If you pull a word from a non-word aligned address, say 5, the processor will have to do two fetches, one for bytes 5, 6, 7 and a second 8, 9, 10, 11, 12, so it will take twice as long.
Addressing bytes individually is useful for all sorts of reasons, but one could easily imagine a processor design that addressed word addressing instead. If you wanted a byte you would get a word, blank out the bytes you don't want, and shuffle the byte to the bottom of the word. In a way that's what's happening, getting a byte is getting a a word, and then picking a byte from it, it's just easier to think about it as a byte at address 10 rather than word 1, byte 3.
Outside the CPU the RAM never gets to see the lower address bits, the RAM is organised as words, it's the CPU/Programmers model that's providing the illusion of byte addressing.
In your example, writing one byte, from a memory word point-of-view, the word has changed. You and I both know that only a few bits of it are different, but regardless, the memory now needs to be refreshed. So that word gets written back to memory - all 64 bits. This would be true, no matter what the minimum addressable size of memory is. When memory was 8-bits wide, all 8 bits would have been written even though perhaps only 1 bit had changed.
From what I recall from my days of Assembler and low-level hardware work, memory is actually accessed in pages. You never really access a single byte, or even the bus-width of the RAM, but rather in blocks (I can’t give you an exact number—particularly since it varies—but the numbers 4KB sound very familiar [maybe I’m thinking of segments, though that’s 64KB]).
The point is that it is terribly inefficient to address a single byte, especially since the next memory address to be accessed is likely to be right next to it. As such, when you access a byte, the system caches a block of RAM (what do you think the various CPU caches are for?) Any changes you make are done to that cached RAM, so that if you write it back, it can write the block nice and quickly. The byte is accessed by itself, but from a cached block; that is, the CPU does not fetch a single byte, but it does return just one.
With today’s systems being so much bigger, I imagine that they would need to cache even more to optimize things (hence larger CPU caches).