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I have just a simple question. Today memory DDR chips are 64 bits wide, and the CPU data bus is also 64 bits wide. But memory is stil organised in single bytes. So, what I want to ask is, when CPU selects some memory adress, it should be one byte, right? Becouse the lowest memory portion you can access is 1 byte. But, if you get 1 byte per 1 adress, why is memory bus 8 bytes wide?

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We refer to our computer architectures as byte-addressable -- meaning, memory is addressed as bytes. That helps us pull 8-bits of data at a time. But, that is not always the norm, and other widths are used.

In fact even as you use a Intel based byte-address computer, the memory you use is usually accessed with a different width (64 bit as in your example).

This helps in addressing larger amount of data with lesser address space.

My answer actually completes here, however, I ramble further to talk about how memory accesses are done which might help think about the abstractions implemented (and maybe also motivate you to read up some more on memories).


If you have seen a DDR-RAM stick, you would recall seeing several chips on a green PCB. These are striped together for a parallel access. That makes your RAM accesses faster.

In front of the RAM module is a Memory Controller. This is designed to access data in a wider bit-width (32, 64, 128 bits -- depending on the design).

When you access a byte from this memory space, the memory controller actually gets a complete "memory word"; here, a word is actually the width of this access from the memory controller.

Which means if its 128 bit width, you always fetch 16 bytes from addresses which are multiples of 16.

So, now what happens when you want a byte at address 18 (= 16+2)?
Well, you get 16 bytes from address 16 and throw away 15 of them!

More interestingly, what happens when you want to write a byte at address 19?
You fetch 16 bytes from address 16, change the 3'rd (19th address) byte, and then write back all these 16 bytes (fun huh?).

All this is quite an effort. The memory controller is designed to manage this and infact works on multiple requests in parallel.

We are not even talking about 'dual-channel' yet :-)


Here is a reference from Wikipedia on DDR SDRAM organization

PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips
with a bandwidth of 3,200 MB/s. As the memory is double pumped,
this means that the effective clock rate of PC3200 memory is 400 MHz.

1 GB PC3200 non-ECC modules are usually made with sixteen 512 Mbit chips,
8 down each side (512 Mbits × 16 chips) / (8 bits (per byte)) = 1,024 MB.
The individual chips making up a 1 GB memory module are usually
organized with 64 Mbits and a data width of 8 bits for each chip,
commonly expressed as 64M×8.

Memory manufactured in this way is low density RAM and will usually be
compatible with any motherboard specifying PC3200 DDR-400 memory.

From the Memory Controller page

Bus width is the number of parallel lines available to communicate with the memory cell.
Memory controllers' bus widths range from 8-bit in earlier systems, to 512-bit in more complicated systems and video cards (typically implemented as four 64-bit simultaneous memory controllers operating in parallel, though some are designed to operate in "gang mode" where two 64-bit memory controllers can be used to access a 128-bit memory device).

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Nice answer. But, if one adress = 8Bytes, why can 32 adress bus still adress 4GB of memory tops? Shouldn´t it be 4G * 64 ? –  user32569 May 7 '10 at 17:51
    
And there is one more thing. When I see output from C compiler, it adress for example char field by bytes. So, I guess there is some chip in CPU that examines next instructions and if there is another Byte from next memorry location, it loads the whole block of memory into cache? –  user32569 May 7 '10 at 18:36
    
@b-gen, When we say byte-addressable, one address is always 8-bits (i.e. one byte). However, a memory controller working on say a 64-bit width will fetch 8 bytes (over 8 addresses) together. But, to be able to address (say) the second 'byte' in those 8 bytes, the addressing is still byte based. The next 8 bytes for instance will be accessed by adding 8 to the address. –  nik May 8 '10 at 1:22
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It's faster to transfer large amounts of data 8 bytes at a time instead of 1. Besides, there's no way to actually address single bytes outside of CPU cache anyways since the last few address bits don't have physical connections anymore (because they're not needed).

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Ok, so if I get you right, you say that now, minimal RAM acess data width is 8 bytes per adress, and the compatibility is preserved via CPU cache? But, what about this scenario?: I want to store 1 byte into RAM, so I actually store it into CPU cache. But, than cache has to write it into memory. (for example if I want to switch to multitask). So, it still has to write 1 byte. How it does if it cannot adress only 8 bytes at the time? –  user32569 May 7 '10 at 17:11
    
BTW: Are you 100% sure about what you wrote? Becouse, they would not add Physical adress extension if few adress bits were disconnected due to 8 byte data cell. –  user32569 May 7 '10 at 17:15
    
In order to write a single byte, it needs to read the existing set of 8 bytes, modify the single byte, then write out all 8 at once. PAE works by adding address bits on the other end. –  Ignacio Vazquez-Abrams May 7 '10 at 22:48
    
+1, good points. –  nik May 10 '10 at 16:45
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I speak with no great expertise but roughly...

Processors retrieve one word at a time (i.e. a 64 bit processor retrieves 8 bytes at a time). However when retrieving a single byte they effectively throw away the other 7 bytes. The memory addressing scheme is still usually thought of as bytes, but if you are pulling data as fast as possible you use word aligned addresses, that is addresses that are divisible by the word length in bytes. In a 64 bit system you'll use addresses 0, 8, 16, 24, etc.

If you pull a word from a non-word aligned address, say 5, the processor will have to do two fetches, one for bytes 5, 6, 7 and a second 8, 9, 10, 11, 12, so it will take twice as long.

Addressing bytes individually is useful for all sorts of reasons, but one could easily imagine a processor design that addressed word addressing instead. If you wanted a byte you would get a word, blank out the bytes you don't want, and shuffle the byte to the bottom of the word. In a way that's what's happening, getting a byte is getting a a word, and then picking a byte from it, it's just easier to think about it as a byte at address 10 rather than word 1, byte 3.

Outside the CPU the RAM never gets to see the lower address bits, the RAM is organised as words, it's the CPU/Programmers model that's providing the illusion of byte addressing.

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In your example, writing one byte, from a memory word point-of-view, the word has changed. You and I both know that only a few bits of it are different, but regardless, the memory now needs to be refreshed. So that word gets written back to memory - all 64 bits. This would be true, no matter what the minimum addressable size of memory is. When memory was 8-bits wide, all 8 bits would have been written even though perhaps only 1 bit had changed.

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From what I recall from my days of Assembler and low-level hardware work, memory is actually accessed in pages. You never really access a single byte, or even the bus-width of the RAM, but rather in blocks (I can’t give you an exact number—particularly since it varies—but the numbers 4KB sound very familiar [maybe I’m thinking of segments, though that’s 64KB]).

The point is that it is terribly inefficient to address a single byte, especially since the next memory address to be accessed is likely to be right next to it. As such, when you access a byte, the system caches a block of RAM (what do you think the various CPU caches are for?) Any changes you make are done to that cached RAM, so that if you write it back, it can write the block nice and quickly. The byte is accessed by itself, but from a cached block; that is, the CPU does not fetch a single byte, but it does return just one.

With today’s systems being so much bigger, I imagine that they would need to cache even more to optimize things (hence larger CPU caches).

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Given the specifics in the question, I tend to disagree with use of the word block in context of 4KB and 64KB sizes in your answer. Cache-lines and cache-memory are at a different level of the hardware hierarchy. (refer en.wikipedia.org/wiki/CPU_cache against the links in my answer) –  nik May 10 '10 at 16:43
    
I used block as a generic term (“chunk” sounded a bit weird). What I was thinking about is a page of memory. Though like I said, it’s been a while, so I don’t remember the exact details too well. I’ll pull out that old, orange Assembler book to see if I can get a refresher. –  Synetech May 10 '10 at 18:42
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