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Usually,the processor has to wait for the memory, recently I came across a question which stated something like,

How will you construct a state-zero machine?

Which memory should I use? I stated Cache.

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Why a -1? I don't find a reason behind it. – Startup Crazy Nov 14 '10 at 11:14
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You would have to use SRAM, whose access speed reaches into the single-digit nanoseconds.

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The SRAM waits for the next clock cycle,slowing its speed.I guess that won't work – Startup Crazy Nov 13 '10 at 8:19
@Fahad -- erm, doesn't that mean that it's faster than CPUs? – RCIX Nov 13 '10 at 8:21
@RCIX:According to what I know,DRAM responds as fast as it can to the change in control input,while SRAM waits for the next clock cycle to respond.Doesn't that mean that DRAM responds faster? – Startup Crazy Nov 13 '10 at 8:31
@fahad: "As fast as it can" may mean multiple cycles (and it usually does). – Ignacio Vazquez-Abrams Nov 13 '10 at 8:33
@Ignacio:Multiple cycles? – Startup Crazy Nov 13 '10 at 12:22
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up vote 2 down vote

Multi-level caches generally operate by checking the smallest Level 1 (L1) cache first; if it hits, the processor proceeds at high speed. If the smaller cache misses, the next larger cache (L2) is checked, and so on, before external memory is checked.

Therefore I would recommed you a CPU with large L1 & L2 cache.

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You actually wouldn't use cache or SRAM. You'd confine your machine to using registers only, which are literally on the CPU itself. This is the basis of RISC vs. CISC computing.

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I think that the instructions are out of the size range of registers – Startup Crazy Nov 14 '10 at 11:13
Well don't forget on a RISC or 64-bit CPU you do have a lot of them, compared with a 32-bit CPU. – ultrasawblade Nov 14 '10 at 13:23
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