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I'm developing a sort of "cache emulator" and I need to know what is the size of the transfer unit between main memory and L2 cache for a core 2 duo processor. Anyone knows it? Thanks.

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"Core 2 Duo" processors are made with the Core microarchitecture design.

Microarchitecture Details

According to the Intel documentation (Vol. 1, 2-15, page 49 of the PDF), L2 cache has a 256-bit internal data path, so this would be from L2 cache to L1 and instruction fetch/decode.

A few pages later (Vol. 1, 2-32), the Intel Core 2 Duo E6850 has a 10.6GB/s internal data path when the processor core is at 3GHz with an FSB of 1333MHz.

ibus-transfer-amt/bus-clock = (256 bits / (8 bits / byte))
     = 32 bytes/clock

bytes-per-sec = (10.6 GB) * (2^30 bytes/GB)
     = 11,381,663,334 bytes/sec

ibus-clk-fq = (bytes-per-sec) / (ibus-transfer-amt/bus-clock)
     ≈ 355,676,979.19 Hz
     ≈ 355.7 MHz

fsb-divisor = (1333 MHz) / (355.7 MHz)
     ≈ 3.75

The Intel documentation also lists the FSB for this processor at 1333 MHz and 10.6 GB/s, so you should be able to calculate that similarly.

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Thank you for the well-researched answer, but my question was a bit different from what you've interpreted. To put it simply: a L2 line is 64-byte wide. Now, it is well-known that when there is a transfer between two levels of the memory hierarchy (due to prefetching or miss/fault), the amount of data transferred is a multiple of the size of the block of the lower level. So, how many cache lines are transferred in response to a miss? One (so two consecutive transfers from memory, according to the data you postes)? Some more? Anyway, I'm rewarding you the bounty anyway :) – akappa Jun 2 '11 at 12:49
The part of the documentation I got the width from is: "256 bit internal data path to improve bandwidth from L2 to first-level data cache". It seems to me that this IS talking about the bus width, not the cache line size, which I know may differ. – Lara Dougan Jun 2 '11 at 15:48
Also 256 / 8 = 32, so if the cache line was 64-bytes wide, then the multiple would be 0.5. – Lara Dougan Jun 2 '11 at 15:50
Of course they may differ, in fact THEY differ - L1 and L2 lines are, in fact, 512 bits wide. But transfer unit between cache hierarchy and bus wideness are two different concepts (wideness tells you how much data you can carry between two levels "at once", while the transfer unit is the amount of data that is exchanged between two levels in response of an event, and usually it is a multiple of the bus wideness), so unfortunately my question still stands :) – akappa Jun 2 '11 at 15:56

If your cpu is 64bit compatible, then each channel is 64 bits wide. Dual channel DDR2 memory should have a 128 bit wide pathway to the cpu. But the bus between the cpu and its l2 cache should be 64 bits wide.

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"bus between CPU and its L2 cache"? Sorry? – akappa May 28 '11 at 0:37
up vote 0 down vote accepted

Okay, I've discovered that, in x86 jargon, an L2 "cache line" is both the unit of storage allocation in L2 caches and the transfer unit between RAM and L2.

In a Core 2 duo, a cache line is 64-bytes wide, so that answers my question :)

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