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  1. I was wondering if the bits of OS, of instruction set, of CPU registers, of data bus from CPU to memory, and of address bus from CPU to memory must be consistent in some sense and how?
  2. When we cay bits of an architecture, which one of the above is it referred to?
  3. When we say bits of a CPU, which one of the above is it referred to?
  4. Why in the table in, the bits of register are sometimes bigger than the bits of the architecture, and sometimes smaller? Aren't they supposed to be bigger?
  5. When we say bits of an OS or application, what does it mean? does it mean? Must they be the same as the bits of instruction set?

Thanks and regards!

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do you mean like a 32 or 64 bit architecture/os/ cpu? – Conrad Frix Jun 18 '11 at 19:19
@conrad: Yes, I do. – Tim Jun 18 '11 at 19:22
  1. The bit-width of any particular stage (registers, data bus, address bus or even instructions) does not have to match the bit-width of any other stage. Whatever operating system that runs on that CPU simply has to be aware of the limitations in each stage, and to take account of it.

  2. Generally when we say 32- or 64-bit we are referring to the number of address lines available to the CPU and this is usually synonymous with the address register bit-width, as this is the most limiting factor. Data can be transferred using a small number of data lines using multiple transfers, but the same cannot be said of memory addresses. Each address has to be physically selectable via address lines and there must be at least enough address lines as there are address bits.

  3. same as number 2.

  4. Registers (especially special data registers such as SSE) can work with more data than the general bit-width of the data bus and while there are instructions that state "take this byte from memory location X and store in register y" there are also instructions that are able to state "take the data from memory locations x and x + 1 and store in special register z" that would use two memory transfers to grab both pieces of data and the instruction would only return after register z was filled with both pieces of data.

    In this way the internal width of data registers does not necessarily have to match the external data bus width as you can simply wait longer for data to be pulled in to the processor. This only applies to data used in memory.

  5. Again we are generally referring to the number of address bits available and therefore how much memory is usable.

You may want to consider looking into programming on a simple CPU such as the Z80 as it is a well known and relatively simple CPU, but will give you a good insight into how it and current CPUs are constrained and used. While modern CPUs are orders of magnitude more complex with many more instructions, the Z80 will give you a good grounding of the basic principles of how a general purpose CPU works.

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32-bit vs 64-bit refers to the address space of the hardware, specifically the CPU. The CPU uses a single 32-bit or 64-bit integer to access memory.

For example, an unsigned 32-bit integer can only access 4 billion addresses, meaning 4 GB of RAM. If the OS is only 32-bit and the CPU is 64-bit, then the CPU will only use 32-bits of addressing space.

Instruction sets, on the otherhand, define the codes that the OS sends to the CPU in order to get work done. These are like move, copy, etc. This happens between registers. There will never be enough CPU registers to account for all of the possible CPU addressing space. This only really makes a difference when talking about RAM anyhow.

The registers are only used for storage of values in intermediate calculations, like storing frequently-used integers. If you look at the MIMIX architecture, it is 64-bit, but has 256 registers. The number of registers is part of the chip spec, not some hardware limitation.

The number and types of registers are chip design optimizations that depend on the intended use of the CPU. More consistent designs (like x86 and x86-64) means that OS developers can generalize more, and more specific ones are developed with a particular OS in mind.

I don't know too much about low-level chip design, but this is as much as I've gleaned from my EE classes as college and from Wikipedia =).

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