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As far as I understand, FSB and RAM clock speed are 2 separate values. So what happens when the FSB clock is quicker than RAM, or FSB is slower?

Is there any buffer for data? Or is the processor just on hold until the data is written? Could you clarify this?

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Firstly, now with on-CPU memory controllers this is much more irrelevant, the CPU is now connected directly to the memory and so the FSB -> Northbridge -> Memory frequencies matter much less as the CPU memory controller frequency is the same as the memory frequency.

Typically though there would be a small buffer for memory requests on the northbridge, but also there are control lines between the CPU and northbridge (or more recently between the CPU and memory) that are "Data Ready" lines that signify when data had been fetched by the northbridge and is now ready to be transferred to the CPU. These types of control lines are similar to a modem that uses a RTS/CTS (Ready-To-Send/Clear-To-Send) mechanism to signify that data is ready and that the receiver is ready for it to be sent.

Because of these control lines and small buffers the actual frequencies of each link between various components can be different. The memory and controller can support one speed, then the northbridge forwards on the data to the CPU at a different speed.

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Digital data is almost always transferred from and to buffers. You would be surprised that most of what a computer does (both the hardware and software) involves just moving data around (between devices and subsystems and between variables and registers).

At the low hardware level you will almost always find simple buffers or registers called "latches" to hold the data while it is being transmitted on the bus, or to the receive the data from the bus. You can almost always assume that digital data is temporarily stored in some manner while it is transferred between subsystems, either at the byte/word level (in bus latches) or even for full disk sectors (on IDE/ATA drives) and Ethernet frames (store&forward switches). These "transient storage" capabilities are distinct from any caching capabilities that a subsystem may have.

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Here is a good article from AnandTech about memory dividers:

In particular, it give a nice primer on the basics of how a memory controller interacts with the memory banks.

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