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I read that this is how a CPU retrieves information from memory.

  1. Send an address on the address bus to the memory.
  2. Send a read control signal on the control bus to the memory.
  3. The memory sends the data at the address on the data bus back to the CPU.

I was wondering, when the CPU sends an address on the memory, is it simply selecting which parts of memory get connected to the data bus, so that when the memory gets a read control signal, whatever is in there automatically gets dumped onto the data bus?

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Modern CPUs don't send addresses anymore; they let the memory controller deal with it. –  Ignacio Vazquez-Abrams Oct 24 '11 at 0:46
    
When did they start doing this? How does the memory controller know what address to send? –  tony_sid Oct 24 '11 at 0:51
1  
They started doing this once CPUs got way too fast for RAM. The memory controller listens for address requests from the CPU and "guesses" which memory locations it will ask for next. –  Ignacio Vazquez-Abrams Oct 24 '11 at 0:53
    
So the memory controller is like a cache? –  tony_sid Oct 24 '11 at 22:45
    
It feeds the cache the data it thinks the CPU will need. –  Ignacio Vazquez-Abrams Oct 24 '11 at 22:52
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1 Answer

In ancient times (1970's and 1980's) that's pretty close to how things generally worked. Essentially, the computer's memory bus would comprise a number of address wires (typically 16, 20, 24, or 32), some number of data wires (typically 8, 16, or 32), and a few control signals. There were a few variations on the control signals, but the typical pattern was that for a read the processor would put an address on the address bus, float the data bus (allowing other devices to drive it), set the control signals in a fashion indicating a memory read, and some time later take whatever signals are on the address bus as the read data, and then release the control signals. For a write, the processor would put the address on the address bus, set the control signals to indicate a write, put the proper data on the data bus, release the control signals indicating a write, and then float the data bus. Some processors allow I/O accesses, which are similar to memory accesses except for special wires which indicate whether a given access is a memory or I/O access.

Typically, the system would have a number of memory or peripheral devices connected to the memory bus, each with a chip-select signal connected to some decoder logic. The decoder logic would assert each chip-select signal whenever a certain range of memory or I/O addresses is selected. Each chip will ignore the contents of the address and data buses except when its chip-select wire is asserted.

Starting in the 1990's (to some slight extent before that), systems added a few more layers between the processors and the memory system. Today's processor memory systems would probably be unrecognizable to people who were only familiar with the ones from the 1980's.

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