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I am trying to find some reference materials to write up something about stacked memory's future. I take this to mean memory that is stacked on the processing chip that allows to faster access time, less latency, etc.

Is this a technology that is likely to be adopted by major manufacturers, and is it worth keeping tabs on as a "future technology?" Maybe it even already exists and I am just unaware of it, but if you google for "stacked memory" you get a few whitepapers and that is about it.

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migrated from Nov 9 '11 at 4:59

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At least as it's normally used, stacked memory is not the same as on-chip memory. Stacked memory is when a separate memory chip is "stacked" on top of the CPU inside of the same package.

This lets you use a (cheap) bulk DRAM part, in conjunction with an (also usually pretty cheap) logic part.

There are two obvious alternatives. One is basically the same chips, but in separate packages. For large items (e.g., DVD players) this is perfectly fine, but for things like MP3 players and cell phones, stacking can save quite a bit of space (and reduce board design costs).

The other alternative is embedded DRAM (or just a large SRAM on the logic chip). The big disadvantage of both of these is that you generally pay quite a bit more per bit of storage. SRAM isn't nearly as dense, and embedded DRAM requires custom fabrication of your entire chip (I.e., you have to design an ASIC instead of using off the shelf CPU and memory parts). That tends to increase your design time and time to market, so unless you gain a pretty substantial benefit otherwise (e.g., from reduced DRAM access time) it's rarely worthwhile.

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The reason is simple : distance.

Light travels about 200.000km per second in a conductor or about 20cm / ns. With clock speeds of 3GHz and we arrive at situations where a you cannot reach the edge of the silicon in a clock pulse, let alone get through pins or balls through conductors to a RAM board many cm's away.

Another reason is space as it reduces board surface and increases function density.

We have been using similar techniques to combine different technologies in the same package. Not just memories but different functions.

So yes this already happens, and it will happen more. Technologies to do this come and go as there are cntinous balances which need to be found. WHen the multicores become relatively smaller and sower, and hence the heat production reduces, we will probably see more of these techniques closer to the CPU's.

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Can you comment on what the technologies are? this is mostly what I am looking for - tangible implementations of stacked design that is happening now and in the near future – Derek Aug 24 '10 at 19:17
It's not really the distance that counts. It's the capacitance - which increases with distance. The slowdown caused by distance is actually worse than merely physical signal propagation time. It's the signal rise time that is more damaging. – slebetman Aug 24 '10 at 19:17
At these frequency capacitance of the wire does not count : you get a model which corresponds to a series inductor and parallel capacitances so you do not 'see' the complete capacitance from your driver, in the end this translates in a model with reduced light speed and a characteristic impedance. Which does matter are the gate capacitances which reduce the flank speeds and of course all other parasitic capacities. You also get nice reflections which corrupt the signal, there is ground bounce when a driver turns on. Fun stuff. You wonder how Intel and AMD can get these things out of the door. – Peter Tillemans Aug 24 '10 at 19:37
@Derek There is a cpu with small feature size on an analog sensor interface/power driver chip. Sensors with analog/logic conbined, etc... see e.g : – Peter Tillemans Aug 24 '10 at 19:54

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