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I'm a bit confused about RAM speeds, latency, and transfer rates.

From what i can make out so far, RAM is rated on it's clock speed and latency. There are a few different latency measurements (the string of 4 numbers, eg, 5-5-5-18), however the only really important number is the last one which measures the overall latency between the access of data between two "random" areas of memory (please correct me if I'm wrong).

My question is this:

how would you calculate the actual RAM latency (ie, in nanoseconds). Is it the tRAS divided by the RAM clock speed or is it the tRAS divided by the processor speed (which doesn't sound right to me, processor shouldn't affect the RAM access like that) or is it something totally different?

Also, how does duel channel and triple channel affect the RAM latency (from what i can gather, it doesn't, it just affects bandwidth) and how exactly does it work? Is it just basically something like striping with RAID for hard drives?

Lastly, is there any difference between access speeds for reading and writing? Does writing take longer and, if so, how is that reflected in the latency timings, or even if it is.

Thanks

-Faken

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1 Answer

up vote 4 down vote accepted

the string of 4 numbers, eg, 5-5-5-18

Memory timings are specified through a series of numbers:

2-3-2-6-T1
3-4-4-8
2-2-2-5

These numbers indicate the amount of clock cycles it takes the memory to perform a certain operation. The smaller the number, the faster the memory.

CL-tRCD-tRP-tRAS-CMD

  • CL: CAS Latency. The time it takes between a command having been sent to the memory and when it begins to reply to it. It is the time it takes between the processor asking for some data from the memory and it returning it.
  • tRCD: RAS to CAS Delay. The time it takes between the activation of the line (RAS) and the column (CAS) where the data are stored in the matrix.
  • tRP: RAS Precharge. The time it takes between disabling the access to a line of data and beginning access to another line of data.
  • tRAS Active to Precharge Delay**. How long the memory has to wait until the next access to the memory can be initiated.
  • CMD: Command Rate. The time it takes between the memory chip being activated and when the first command may be sent. Sometimes this value is not provided. It's usually T1 (1 clock cycle) or T2 (2 clock cycles).

CAS latency is arguably the most important number. Memory with CL = 3 will delay three clock cycles to deliver data; memory with CL = 5 will delay five clock cycles to perform the same operation.

The period of each clock cycle can be calculated:

T = 1 / f

Say you had DDR2-533 memory running at 533 MHz (266 MHz actual clock), that means the clock period is 3.75 ns. If this DDR2-533 memory has CL=5, it would delay 18.75 ns before delivering data, if it had CL=3, it would delay 11.25 ns.

Bear in mind memory also implements burst modes, so if the next requested data address is sequential from the first, there are no delays in getting to the "next" data.

Is it just basically something like striping with RAID for hard drives?

I believe so, yes. Dual and Triple channel (memory must be installed in pairs or triples) are about bandwidth.

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