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In SMT (simultaneous multithreading) processors which threads share the TLB, how does TLB differentiate one thread's access from the other one? Each thread has its own set of pages loaded into memory, and independent threads do not share pages. I would guess there is some kind of hardware support for that in TLB, like some extra bits. But I would like to know more details.

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If threads share a TLB, there is no need to differentiate one thread's access from another one. If threads share a vm, they have the exact same view of memory. If they don't, then they don't share a TLB.

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if threads are from different processes, then they don't have the same view of memory. So their virtual to physical page mapping is different. In SMT processors, two (or more, depending on implementation) threads from different processes can be run at the same time. So as far as I know, they share the same TLB. – aminfar Jan 27 at 4:06
There are two different basic TLB designs. In one, the TLB is per-virtual-core, and the entire TLB is flushed if the vm changes. In the other, the TLB can be shared among cores or not, is not flushed when the vm changes, but contains a tag indicating which vm the entry is for. – David Schwartz Jan 27 at 4:09
@aminfar, AFAIK if the threads are from two different processes, then I don't think that's any different than 2 processes sharing the TLB. Some cpus support sharing (TLB entries are marked to identify the process to which it belongs), others clear the TLB on context switch. – Peon Jan 27 at 4:13
take a look at www.cs.washington.edu/research/smt/papers/os.ps, section 2.2.2 to see what I am saying. – aminfar Jan 27 at 4:16
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