In SMT (simultaneous multithreading) processors in which threads share the TLB, how does the TLB differentiate one thread's access from the other one? Each thread has its own set of pages loaded into memory, and independent threads do not share pages. I would guess there is some kind of hardware support for that in TLB, like some extra bits. But I would like to know more details.
If threads share a TLB, there is no need to differentiate one thread's access from another one. If threads share a vm, they have the exact same view of memory. If they don't, then they don't share a TLB.