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Can someone explain if there is any difference between the intel64 and amd64 architectures?

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migrated from Jan 29 '12 at 18:54

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IA64 = the Intel/HP Itanium VLIW architecture. AMD64 is the AMD developed extention of the standard x86 instruction set. – talonmies Jan 29 '12 at 17:33
Marketing. AMD developed it, then licensed it to Intel. AMD is licensing x86 from Intel, and Intel is licensing x64 from AMD. This ensures that neither can sue the other without losing the rights to sell their entire cpu lineup, as they'd be shooting themselves in the foot. – Marc B Jan 29 '12 at 17:33
Do you mean x86-64, or IA64? The prior is the same as AMD64 (literally the exact same instruction set, or you would need to re-compile all applications for one CPU or the other), and the latter is a completely different CPU architecture. – Breakthrough Jan 30 '12 at 12:41
I mean x86-64. Intel initially used the names IA-32e and EM64T before finally settling on Intel 64 for their implementation. – Mayhem Jan 30 '12 at 12:50

At Wikipedia's x86 page you can read

In 1999-2003, AMD extended this 32-bit architecture to 64 bits and referred to it as x86-64 in early documents and later as AMD64. Intel soon adopted AMD's architectural extensions under the name IA-32e which was later renamed EM64T and finally Intel 64.

In other words, the differentiator is mainly marketing. There are Intel- and AMD specific extensions to the instruction set, but as long as you're writing programs in user space, you don't generally need to know the difference.

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up vote 8 down vote accepted

From what I've read extended Memory 64-bit Technology (EM64T) is Intel‘s implementation of AMD‘s AMD64 and the differences between the Intel64 and AMD64 are:

  • EM64T’s BSF and BSR instructions act differently when the source is 0 and the operand size is 32 bits. The processor sets the zero flag and leaves the upper 32 bits of the destination undefined.

  • AMD64 supports 3DNow! instructions. This includes prefetch with the opcode 0x0F 0x0D and PREFETCHW, which are useful for hiding memory latency.

  • EM64T lacks the ability to save and restore a reduced (and thus faster) version of the floating-point state (involving the FXSAVE and FXRSTOR instructions).

  • EM64T lacks some model-specific registers that are considered architectural to AMD64. These include SYSCFG, TOP_MEM, and TOP_MEM2.

  • EM64T supports microcode update as in 32-bit mode, whereas AMD64 processors use a different microcode update format and control MSRs.

  • EM64T’s CPUID instruction is very vendor-specific, as is normal for x86-style processors.

  • EM64T supports the MONITOR and MWAIT instructions, used by operating systems to better deal with Hyper-threading.

  • AMD64 systems allow the use of the AGP aperture as an IO-MMU. Operating systems can take advantage of this to let normal PCI devices DMA to memory above 4 GiB. EM64T systems require the use of bounce buffers, which are slower.

  • SYSCALL and SYSRET are also only supported in IA-32e mode (not in compatibility mode) on EM64T. SYSENTER and SYSEXIT are supported in both modes.

  • Near branches with the 0×66 (operand size) prefix behave differently. One type of CPU clears only the top 32 bits, while the other type clears the top 48 bits.

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Where did you read that text from? – Tom Wijsman Jan 30 '12 at 16:39
Well, some forums/blogs + wikipedia ( Also I looked over some manuals from Intel and AMD. – Mayhem Jan 30 '12 at 17:19

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