Let's say that we're looking at a DRAM with typical timing parameters (those of interest are listed below) with read and write latencies of ~20-50 nanoseconds. How would one go about changing the timing parameters to cause the read and write latencies of the DRAM to increase? Specifically, let's say that we wanted read and write latencies of ~1 microsecond. The parameters I have to work with are the following (if others are important and not listed, please mention them; any of these which are unimportant or which don't make sense can be ignored):
* tCCD = CAS to CAS command delay (always = half of burst length) * tRRD = Row active to row active delay * tRCD = RAW to CAS delay * tRAS = Row active time * tRP = Row precharge time * tRC = Row cycle time * CL = CAS latency * WL = Write latency * tWTR = Write to read delay
The reason I'm asking is that I want to do a small simulation to investigate the effect of varying memory access latencies on program performance for various memory access patterns. My knowledge of memory hardware is woefully limited; given the parameters above, I'm thinking that memory latency for a single access would be something like tRAS + CL to select a row/column, plus WL? I really apologize if these aren't common timing parameters. Thanks in advance!
Come to think of it, if I have a set of timing parameters p1, p2, ..., pN, with know read/write latency X, can I get a new set of parameters p1', p2', ..., pN' for a desired read/write latency Y > X by taking p1' = (Y/X)p1, p2' = (Y/X)p2, ..., pN' = (Y/X)pN ? It seems like I should, since if read/write latencies are some linear combination of underlying DRAM timing parameters, I should be able to simply scale the parameters and get an equivalent scaling in the derived quantities... right?