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We know to minimize delay of cache structures in microprocessors, the bitline wire length and wordline wire length should be relatively the same. So in other words, cache modules in processors should be square shape rather than rectangular shape to minimize delay. However, we know that if we want to realize a naive cache module, it is highly likely to end up having a rectangular cache. My question is what techniques are used to make square-shape caches in real-world designs.

An example: let's say we have a 16KB direct-mapped cache with 64B (512 bits) of cache line. So we will have 256 entries. if we assume each bitcell is a square, then the worldline length is twice as long as the bitline length. How can you restructure this cache so that bitline and wordline have the same size?

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Real world designs don't usually have square cells. They can also divide the cache up into blocks so within each block the lines have equal lengths. If you look at a modern CPU die you can see the cache divided up into blocks fairly easily.

enter image description here

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yeah, to put in your terminology, my exact question is that how to make those "blocks" square. Also, to make it easier to discuss, let us focus on L1 cache (not shown in your picture) which is much smaller, although my question is also relevant to L3 caches (shown in your picture). – aminfar Feb 7 '12 at 17:46

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