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I have been reading a lot about IRQs, and it seems there is conflicting and out of date information. Some of it dating back to Windows 95. Here is what I'm confused about.

  1. Are both software interrupts and hardware interrupts managed and dispatched by the interrupt vector table. If not how are then controlled differently.

  2. I read there is a difference between PCI mode IRQs and ISA mode IRQs, is this true? If so how do you set the mode, and how do they function differently?

  3. Now that we have PCI express, do they use PCI mode IRQs (if they exist), how do they work (interrupt wise).

EDIT 4. Looking at this picture it appears that are many IRQs and that they are mapped to memory. What are the implications of this? There are way more than 16 IRQs. I know that APIC allows for more, but this many?

enter image description here

Thanks in advance :-)

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1 Answer 1

There aren't different modes, there is different hardware on the old ISA bus and the PCI bus. The ISA bus provided 16 IRQ lines on the bus that devices could use to signal for attention. The programmable interrupt controller ( actually a pair of cascaded 8259A chips ) responded to these lines by prioritizing them and signaling the CPU when one was active. This caused the CPU to invoke an interrupt service routine. IRQs 0-7 triggered int 8-F, and IRQs 8-15 triggered int 70-77. Interrupts could also be triggered via the software int instruction, and caused the CPU to call a routine pointed to by the corresponding slot in the interrupt vector table.

Instead of 16 IRQ lines shared by all devices on the bus, PCI provided 4 different IRQ lines to each slot on the bus named INTA-INTD, allowing each device to have up to 4 different IRQs for its own use. In practice, devices only use INTA, which the hardware routes to specific IRQs.

The numbers you see in the image are not memory addresses, they are simply the hexadecimal representation of the IRQ number.

The APIC supports 256 interrupt vectors.

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Cool :-), but where does PCI express fit into all of this? There was was once a mixing of ISA and PCI buses on the motherboard how where these combined? Also, does the increase in interrupt vectors with APIC, where are the new ones allocated. I'm assuming ISA stays the same, PCI, stays the same, or does either one get an increase? –  rubixibuc May 1 '12 at 4:01
    
Does this mean that the APIC de-muxes 256 vectors to 16 (which I guessed from your 8-F, 70-77 which I don't understand) physical wires that enter the CPU chip as IO? Is this number a constant for all x86 architecture? –  PPC Aug 1 '12 at 20:59
    
@PPC, no, the APIC directly supports 256 interrupt vectors that are signaled to it via a serial protocol over, iirc, a two wire bus connecting all of the cpus, the northbridge, and any IO APICs. The old 16 IRQs were physical lines on the ISA bus connected to 8259A PICs which mapped them to software interrupt vectors 8-F and 70-77. –  psusi Aug 6 '12 at 23:27
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