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How come, for example, a 2.66 GHz dual-core i5 will be faster than a 2.66 GHz Core 2 Duo (also dual-core)?

Is this because of newer instructions that can process information in less clock cycles? Other architecture changes?

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Wow both breakthroughs and david's are great answers...I dont know which to pick as correct :P –  agz Jan 30 '13 at 2:42

2 Answers 2

up vote 20 down vote accepted

It's not because of newer instructions usually. It's just because the processor requires fewer instruction cycles to execute the same instructions. This can be for a large number of reasons:

  1. Large caches mean less time wasted waiting for memory.

  2. More execution units means less time waiting to start operating on an instruction.

  3. Better branch prediction means less time wasted speculatively executing instructions that never actually need to be executed.

  4. Execution unit improvements mean less time waiting for instructions to complete.

  5. Shorter pipelines means pipelines fill up faster.

And so on.

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I believe the Core architecture has a 14-15 stage pipeline (ref), and the Nehalem/Sandy Bridge has roughly a 14-17 stage pipeline (ref). –  Breakthrough Jan 30 '13 at 0:10
Shorter piplines are easier to keep full and reduce the penalties of pipeline flushes. Longer pipelines generally permit higher clock speeds. –  David Schwartz Jan 30 '13 at 0:11
That's what I mean, I think the pipeline depth itself has remained the same or has increased. Also in the Intel 64 and IA-32 SW Dev Manuals, the last mention of a pipeline change is in Vol. 1, Ch. 2.2.3/2.2.4 (the Intel Core/Atom microarchitectures). –  Breakthrough Jan 30 '13 at 0:13
The effort to raise clock speeds has resulted in longer pipelines. That got ridiculous (as many as 31 stages!) towards the end of the NetBurst era. These days, it's a delicate engineering decision with advantages and disadvantages both ways. –  David Schwartz Jan 30 '13 at 0:19

The absolute definitive reference is the Intel 64 and IA-32 Architectures Software Developer Manuals. They detail the changes between architectures, and they're a great resource to understand the x86 architecture.

I would recommend that you download the combined volumes 1 through 3C (first download link on that page). Volume 1 Chapter 2.2 has the information you want.

Some general differences I see listed in that chapter, going from the Core to the Nehalem/Sandy Bridge microarchitectures are:

  • improved branch prediction, quicker recovery from misprediction
  • HyperThreading Technology
  • integrated memory controller, new cache hirearchy
  • faster floating-point exception handling (Sandy Bridge only)
  • LEA bandwidth improvement (Sandy Bridge only)
  • AVX instruction extensions (Sandy Bridge only)

The complete list can be found in the link provided above (Vol. 1, Ch. 2.2).

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