Any system with more than one "level" of cache or memory technically classifies as a NUMA design, so this might be a misnomer depending on your perspective. To fully leverage any modern processor's full power, one must be considerate of the cache design & size, or consider a cache-oblivious algorithm.
Indeed, the closest thing to "shared" memory in a modern computer is the concept of L2/L3 cache, or cache lines shared between all cores on a processor die. While some servers have specific memory controllers which can handle multiple reads/writes at once, this is very rare to see in a consumer environment, and they still implement a NUMA design for higher throughput. This requires significant processing power/time to ensure the integrity of the memory contents in different segments.
Uniform memory access made sense back when computer clock speeds were relatively slow, or equal to, that of DRAM cycle times. Now, however, our computer RAM is significantly slower (paying a penalty of hundreds of clock cycles for memory accesses), thus why we segment our memory map with subsequent layers of faster and faster memories (RAM, several cache levels, and processor registers).