In its simplest form, a makefile is pretty much just a list of commands, separated by labels. By convention, the label
all is usually used as a sort of default.
The makefile consists of:
label1: [dep1 ... depN]
label2: [dep1 ... depN]
A traditional beginner's mistake is to indent using spaces, but make wants commands to be indented using a single tab character.
For a simple case, you can ignore the dependencies.
So, the simplest makefile will be something along the lines of:
<tab> cc -o hello -Wall hello.c
make in a directory where a file like the above exists as
Makefile will cause
cc -o hello -Wall hello.c to be invoked. If your make is really picky, you may need to explicitly say
make all, but that should not be necessary.
There's about a million possibilities with makefiles, but the above should get you started. Strictly speaking the above examples are for GNU make, but makefiles are so ubiquous I don't see other implementations doing the basic use case very differently.