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I'm trying to find the link between Memory BARs (Base Address Registers) and Physical Memory in a PCI Express Transactions. In my last question I started to understand what happens when a CPU reads/writes at a certain memory address, now I need to go deep into the PCI Express Transaction.

I need to understand if physical RAM is involved in every PCI Express Memory Read/Write Transaction.

1) Does the physical memory addressed by a device Memory BAR reside in the device itself? Or does it reside in the RAM?

2) When I start a Memory Read/Write transaction to a PCI Express device without inboard physical memory, specifying a memory address, how can the device access it if it's not mapped to an inner physical memory? When my device returns a transaction packet with data, does the root complex both give the data to the cpu and insert it into physical RAM?

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up vote 4 down vote accepted

Main system RAM has nothing to do with a BAR. The BAR simply configures the device to decode access to those addresses. Normally the device contains a number of configuration registers. The BAR allows the CPU to access these registers as if they were a block of ram, but there isn't actually ram there. The PCIe root complex is configured to route most memory access to RAM, and access to a block of addresses, typically in the 3-4 GB area, to the PCIe bus instead. The BAR in a given device configures it to respond to a specific block of those addresses.

On the other hand, some devices, most notably video cards, actually do have their own ram on board that is accessed via the BAR.

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Thank you for your answer, but something remains unclear to me. When I start a Memory Write transaction to a PCIe device, am I really writing into a register inside the device? Or is somebody writing inside the PC RAM? – Jacopo Reggiani Jun 14 '13 at 16:03
@JacopoReggiani, you are writing to the device. Whether that is a register, or actual ram on board the device is up to the device itself. As my first sentence said, it has nothing to do with main system ram. – psusi Jun 15 '13 at 19:05
Most systems use subtractive logic to decode where a memory operation is routed. Main system memory (DRAM) will be mapped to a specific set of ranges in the memory controller. If an address is outside of this range then it is routed to the I/O busses based on their BARs. In x86 if an I/O is still unclaimed it is typically routed to the DMI/Legacy supporting interface. Thus PCIe I/Os should be unclaimed by the DRAM controllers and routed to the appropriate PCIe bus whose BAR overlaps with the MMIO. – Jon Brauer Dec 2 '13 at 20:58

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