I'm trying to find the link between Memory BARs (Base Address Registers) and Physical Memory in a PCI Express Transactions. In my last question I started to understand what happens when a CPU reads/writes at a certain memory address, now I need to go deep into the PCI Express Transaction.
I need to understand if physical RAM is involved in every PCI Express Memory Read/Write Transaction.
1) Does the physical memory addressed by a device Memory BAR reside in the device itself? Or does it reside in the RAM?
2) When I start a Memory Read/Write transaction to a PCI Express device without inboard physical memory, specifying a memory address, how can the device access it if it's not mapped to an inner physical memory? When my device returns a transaction packet with data, does the root complex both give the data to the cpu and insert it into physical RAM?