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When manufacturers mention the speeds of smartphone processors, is it right in my understanding that the speeds between smartphone processors and desktop processors are comparable?

In other words, can I hypothetically swap the Snapdragon Krait 1.5 GHz quad-core processor with my 1.2 GHz Celeron desktop processor and expect faster responses?

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In short: Yes you can use ARM CPU to run an operating system (one example will be Raspbian from running on Raspberry Pi - So assuming you can create an OS that can run on that specific CPU (and whatever other hardware connected to it), it will be able to run it. Faster or not - need to do side by side testing to be sure. – Darius Sep 3 '13 at 7:45
They're not in any way comparable, even with the same ISA - a pentium M used to beat the crap out of a PIV twice the clockspeed. Also see pr ratings . You also can't run software for one ISA (x86) on another ISA (arm). I won't even call it apples and oranges - its comparing beefstake and durian – Journeyman Geek Sep 3 '13 at 7:52
I'd like to see a grep or gcc benchmark comparison – artistoex Sep 3 '13 at 9:44
@artistoex grep is likely I/O bound, and gcc is hardly appropriate for CPU benchmarking, either. There are benchmarks out there, but keep in mind that artificial benchmarks typically don't measure every aspect important to real-world operation. – Bob Sep 3 '13 at 9:55
@bob grep and gcc sessions are very common performance evaluation approaches (they are used in most of the SEPC suites and I've seen them at a number of occasions in H&P, Computer Architechture). Anway, I'd like to see this question appraoched from a pragmatic angle: Given the best platforms and compilers available, how many computing results can you get out of a processor? – artistoex Sep 3 '13 at 10:16

Lets start with the obvious things and work our way down.

Physically different form factors of systems have different ways of interfacing with your motherboard - you can't get a desktop LGA or PGA processor into a smaller laptop socket with a different pinout. Phones and some laptops also use soldered on BGA processors. You'd be trying to fit a 1/4 inch peg into a 1/2 inch hole.

You'd also need 'motherboard' level support - with PCs this would be in the bios/uefi firmware to be able to bootstrap the processor. Intel's sandy bridge and ivy bridge processors shared a socket, and could be swapped between boards of either generation, but sandy bridge boards needed a firmware update. As such your firmware would need to be able to communicate with either.

Secondly, they run different Instruction Set Architectures . Assuming you had a magical motherboard with a chipset that could speak to both a specific ARM and Intel chip... none of your software would work without a compatibility layer. You could in theory outfit an OS to run software from another architecture, like rosetta, but simply swapping chips would result in breakage in software. And this is assuming a hypothetical magical system, that is compatible with two completely different chip designs!

In short, if you had two chips with ISA compatibility, identical pin outs and firmware support, you could swap them. If you tried to put an arm chip into a intel board, or a intel processor into a arm phone (which would be monumentally stupid considering phones have soldered on processors), things would very likely not work. Things might burn out since pinouts are different. It simply would be a disaster.

Finally, clock speeds of processors these days has less and less relevance to actual performance. There was a massive dip in processor clock speed post pentium IV on intel processors. Comparing clock speeds is useful within the same family and generation of processors taking into account cache and core count. Comparing an arm processor and a intel processor of identical speeds properly would mean throwing carefully designed sets of work at them to see how they perform.

In short

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One does not simply switch chips between ISAs or formfactors without a full engineering facility.

Edit: As of 2014, AMD's planning a family of systems with pin compatible arm and x86 core options, under the codename 'skybridge'. There's nothing concrete outside press releases, and various articles, but this would be the closest thing to what the OP asked for.

These would be pin compatible processors with chipsets that can handle either arch, and in theory you could stick an appropriate processor of a different architecture, in the right sort of socket, or desolder and solder on a new, different processor.

However, this is exactly what I mean by needing a full engineering facility, and precisely what I would mean by a magical motherboard.

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A little more on RISC: The RISC instruction set is (for the most part) a subset of the full x86 instruction set. Meaning that even if you did manage all of this (by using something like the Pi board) the real world performance would be asymmetrical due to the fact that the number of machine instructions for a RISC operation are not 1:1 with x86 PC architecture. For example, it may do the equivalent of 4+4+4 rather than 4*3 because it doesn't have a multiplication operation but it can still get the same functionality with the addition operation (this is an example, RISC does have multiply). – krowe Aug 26 '14 at 4:23
Note though, I never actually talk about risc and cisc, since in the modern context, those do not matter. Modern x86 processors are internally Risc-y, while many arm chips have cisc-like characteristics. There have also been popular hardware and software level translations. – Journeyman Geek Aug 26 '14 at 5:12
There is no such thing as "the RISC instruction set", unless you're referring to the Berkeley RISC, which was a research project that eventually spawned the SPARC architecture, and is only of historical significance at this point (as is the SPARC architecture, in most areas). Also, your thesis that the architectural incongruity between RISC and CISC based ISAs would be the main performance hit is simply incorrect. The ISA translation layer you'd need, either in software or firmware, would itself be the bottleneck, whether CISC<->RISC or not. – allquixotic Aug 26 '14 at 5:24
Basically just adding a translation layer, regardless of what it's translating "to" and "from", would add enough overhead as to make such a solution, at best, about as fast as a fairly slow virtual machine. It wouldn't approach the speed of hardware-assisted x86(_64) VMs running on x86(_64), because those don't do ISA translation; they just poke little holes in the code to do VM-specific stuff here and there, but otherwise let the guest code run directly on the CPU. When you're talking about hardware or firmware supporting multi-arch, that's high overhead, even compared to a VM. – allquixotic Aug 26 '14 at 5:26

Short answer:

You are asking to compare apples and oranges. It's not a fair comparison.

Long answer:

There are a ton of factors involved other than raw CPU clock speed, mostly hardware related. Peripherals, memory, and bus speed and architecture are biggies. Another is how the CPU silicon is constructed; ARM CPUs are typically simpler, and don't have performance-enhancing features found in x86 chips that boost the power requirements and chip die size.

Generally speaking, the thermal and power requirements of the smartphone will always make it possible for desktop CPUs to be better purely in terms of die size (form factor). The question is how much "better" is needed, and will we reach a plateau point?

The Processors used in mobile phones (cellphones/feature-phones/smartphones) are a different category (they are mostly ARM processors) than PC's and are optimised for even lower power and cooling resources.

Tablets/slates/pads/fondleslabs form a middle ground where traditional desktop/laptop CPU architectures (e.g. x86) and traditional small-device architectures (e.g. ARM) are both used. You can view this as convergence from both directions.

A necessary consequence is that mobile processors are slower but they probably incorporate power-saving tricks that are not so much used in desktop PCs (I think variable CPU clock-rates started in mobile processors).

Processing power is still orders of magnitude higher on even older desktops compared to the most advanced phones on the market. An Intel Atom processor is significantly faster than anything in any smartphone.

The thinking behind building a smartphone processor is something like 95% make it as low power as possible and 5% make it fast(Not real numbers of course). It has to be in a device and powered on the entire time and last a whole day, the power usage has to be tiny. Desktop PC processors are very much performance oriented.

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Yes, speeds for smartphone and desktop processors (as well as any other processors) are comparable in such a way, that 1 Hz equals 1 computational operation per second. In this way - assuming both CPUs have the same or similar instruction set and bus width - a 1.5 GHz quad-core processor can compute faster than a 1.2 GHz Celeron.

Practically you cannot swap the Snapdragon with the Celeron, as the hardware interfaces are incompatible.

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-1 This is sooo wrong... The days that 1 clock-cycle equaled 1 operation are about 50 years behind us. That hasn't been true since the first pipe-lining CPU's where invented in the 70's. All CPU's do multiple operations per clock. How many varies greatly from architecture to architecture and even model to model within the same architecture. – Tonny Sep 3 '13 at 9:31
@Tonny Or take multiple clock cycles for a single instruction. It really depends on the instruction. But, yes, you won't see that kind of one-to-one correspondence. – Bob Sep 3 '13 at 9:35
There is still a one-to-one correspondence. 1 Hz equals 1 switching operation on the logic level. :-) (I know the word is tautology) – artistoex Sep 3 '13 at 9:42
@Bob Obviously but I didn't want to complicate matters too much. – Tonny Sep 3 '13 at 12:18
@artistoex Not true. Any modern processor sub-divides the external clock (which the poster referred to) into multiple internal clocks at higher frequencies (or lower, that is also possible). These internal clocks drive logic circuitry clocking the micro-operations in the CPU. But still there is no 1-on-1 relation between clock-pulse and operation. Operations can take multiple clock-cycles or be variable in length. It is also common to have a operation started by 1 clock and synchronizing its end by another. So it is far more complex than 1 CPU cllock-cycle=1 operation – Tonny Sep 3 '13 at 12:26

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