After reading how processors use pipelines (from various articles: wikipedia, SU, and other places), I'm a bit confused on certain parts of what I've read, so I would just like to share what I've come to understand and if someone can just clarify that the following is correct (please let me know if any of it's wrong),
cycle = clock cycle
ICR = Instruction Completion Rate
IT = Instruction Throughput
IL = Instruction Latency
IL is the number of nanoseconds taken for a single instruction to pass through the whole pipeline (so the lower the IL, the higher the ICR).
Each stage of a pipeline takes one cycle to complete.
Assuming that: a pipeline doesn't experience any "bubbles", cache misses, etc; the pipeline is 5 stages deep, the processor is running at a clock speed of 2 GHz (that's 0.5 nanoseconds per cycle).
The processor will be able to process 800'000'000 instructions in one second (ignoring the fact that the pipeline needs to first fill with instructions, in order to reach it's maximum IT).
If a pipeline is 10 stages deep, an instruction will have an IL of 10 cycles.
The maximum IT a single core, non-superscalar architect processor can achieve is, 1 instruction per cycle.
A processor's cycle period is determined by the slowest stage of its pipeline.
The shorter the period of time each stage of a pipeline takes the higher the IT & ICR.
The perfect pipeline has a: low IL, high pipeline depth (but prevents "bubbles", cache misses, etc), high clock speed, high IT & high ICR.