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Firstly, this is true, right? I feel that reads will always be faster than writes, also this guy here does some experiments to "prove" it. He doesn't explain why, just mentions "caching issues". (and his experiments don't seem to worry about prefetching)

But I don't understand why. If it matters, let's assume we're talking about the Nehalem architecture (like i7) which has L1, L2 cache for each core and then a shared inclusive L3 cache.

Probably this is because I don't correctly understand how reads and writes work, so I'll write my understanding. Please tell me if something is wrong.

If I read some memory, following steps should happen: (assume all cache misses)

    1. Check if already in L1 cache, miss
    2. Check if in L2 cache, miss
    3. Check if in L3 cache, miss
    4. Fetch from memory into (L1?) cache

Not sure about last step. Does data percolate down caches, meaning that in case of cache miss memory is read into L3/L2/L1 first and then read from there? Or can it "bypass" all caches and then caching happens in parallel for later. (reading = access all caches + fetch from RAM to cache + read from cache?)

Then write:

    1. All caches have to be checked (read) in this case too
    2. If there's a hit, write there and since Nehalem has write through caches, 
write to memory immediately and in parallel
    3. If all caches miss, write to memory directly?

Again not sure about last step. Can write be done "bypassing" all caches or writing involves always reading into the cache first, modifying the cached copy and letting the write-through hardware actually write to memory location in RAM? (writing = read all caches + fetch from RAM to cache + write to cache, written to RAM in parallel ==> writing is almost a superset of reading?)

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Please don't cross-post between SE sites. Either flag a mod to request and/or wait for a mod to migrate your other question here. If you want it here and not there, since you've already posted both places, please consider going and deleting it from SO. –  Ƭᴇcʜιᴇ007 Nov 12 '13 at 20:02
Reading something is passive, writing (changing) something is active. Activity is almost always harder than passivity. ;) –  Ƭᴇcʜιᴇ007 Nov 12 '13 at 20:17
@user2898278 - Do you have any possible sources more reliable then a random blog? –  Ramhound Nov 12 '13 at 20:23
You have got something elementary wrong here. Every bit of data is addressed...there's no trickling down cache levels looking for data as if you were guessing. –  M.Bennett Nov 12 '13 at 21:15

1 Answer 1

Memory must store its bits in two states which have a large energy barrier between them, or else the smallest influence would change the bit. But when writing to that memory, we must actively overcome that energy barrier.

Overcoming the energy barrier in RAM requires waiting while energy is moved around. Simply looking to see what the bit is set to takes less time.

For more detail, see MSalters excellent answer to a somewhat similar question.

I'm not certain enough of the details of how caching interacts with RAM to answer that part of the question with any authority, so I'll leave it to someone else.

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Thank you for this. I now better understand why "pure" writes would be slower than pure reads. But how much difference do the electronic factors make? I mean would the difference purely due to electronic factors be around 1.5 times between read and write bandwidth? Any ideas? (by pure, I mean excluding caches) –  user2898278 Nov 12 '13 at 22:16
+1 for digging up that excellent SU link. :) –  Ƭᴇcʜιᴇ007 Nov 12 '13 at 23:30

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