As I wrote in my answer to that question the received folk wisdom on the subject — as unfortunately exemplified by other answers there (and elsehere in SuperUser) — is stuck in the world as it was around 1991, despite the wealth of technical references available explaining how it is now otherwise.
You wouldn't have been this confused if you had read my answer, because you wouldn't be asking about "BIOS loaded from ROM" in the first place.
Your "BIOS chip" is not ROM; there is no machine code between processor startup and the first instruction in firmware; and the "M" in both "RAM" and "ROM" means "memory".
As I wrote before, in modern PCs, the machine firmware is held in non-volatile RAM. It's not ROM as it used to be. See the previous answer for details of the NVRAM chip connected to the LPC bus. (For example: On a machine sitting disassembled beside me as I type this, the NVRAM holding the firmware is a Pm49FL004T, an LPC Flash RAM chip.)
32-bit CPUs don't start up in real mode, and don't start with an address that is below the 1MiB line. That's decades out of date rubbish from the times of 16-bit x86 processors. They start in what is colloquially known as unreal mode, and again in my prior answer I gave the details of what has actually been the case since the advent of the 80386. They load their first instruction from an address that is in fact right at the top of the 32-bit address space,
In my prior answer I told you in detail where the machine firmware is principally mapped into physical address space on 32-bit and 64-bit x86 machines. Remember: Both RAM and ROM are memory. Physical addresses are memory addresses, on the system bus. They can address either RAM or ROM. (They can even address other things as well, but that's just complicating this discussion.) The physical address
FFFFFFF0 is 16 bytes below the top of the 512KiB range where the top 512KiB of the firmware, in non-volatile RAM, is always mapped on the system bus by the "chipset".
There's no "loading" from some mythical ROM chip that goes on at processor initialization or reset. The chip holding the firmware is non-volatile RAM. It retains its contents, written when it is "flashed", across power cycles. And the CPU just reads the firmware instructions and data from it, over the system bus and over an LPC bus (and possibly an LPC/FWH bridge) connected to the system bus via the chipset, using a physical memory address.