I'm not sure about your level of expertise on Computer Architecture, however the Core i5 you've mentioned here implements a form of multi-threading known as Simultaneous multithreading (SMT). Intel's trademark for their implementation of SMT is hyperthreading.
Apart from SMT there are other forms of multi-threading, temporal multi-threading being one. For instance fine grained temporal multi-threading where the processor may switch between different threads every cycle and thus enable pseudo-parallel execution of several programs. Similarly there can be coarse grained temporal multi-threading where a processor may switch between threads when it hits a high latency operation such as a main memory access on the current thread. The exact switch points can vary based on implementation and requirements, such as fairness or real time deadlines.
SMT deviates from the context switch philosophy for multi-threading in that it actually has two or more threads executing on one processor at the same time. While the implementation can vary, the primary goal is to exploit the functional units in the processor which are idling if only one thread was executing, and also to exploit the wide issue superscalar nature of the processor. You can imagine temporal multi-threading as time slicing the processors resources, while SMT as spacial slicing of the resources.
A detailed analysis can be found in Tullsen's 1995 paper: