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From http://en.wikipedia.org/wiki/Instruction_set

CISC processors include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many instructions on other computers. Such instructions are typified by instructions that take multiple steps, control multiple functional units, or otherwise appear on a larger scale than the bulk of simple instructions implemented by the given processor.

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In very long instruction word (VLIW) architectures, which include many microcode architectures, a single instruction includes multiple simultaneous opcodes and their operands.

CISC and VLIW seem to me the same concept, in that an instruction includes multiple operations (i.e. opcodes). So are they the same concept?

How do you define a single operation (i.e. opcode) is, when telling if an instruction has multiple operation (i.e. opcodes)?

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2 Answers 2

Modern CISC processors have multiple execution units. They also have a lot of extra circuitry and logic to try and distribute the instruction stream amongst those execution units.

VLIW is an attempt to have the compiler do some of this work and use the saved circuity for even more execution units, cache or other resources.

An example would be Itanium in which instruction words are 128bits and contain three instructions. This lets the compiler do some of the work in pairing up instructions to execute together.

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An instruction is a single order that must be done logically before the next one. If an instruction contains more than one operation, such as in a VLIW instruction, these are meant to be done at the same time. And in a VLIW instruction each operation slot corresponds to a hardware processing unit (a combination of a FPU and an ALU) these are statically assigned by the instruction. Where as in a CISC or RISC the processor may choose any free processing unit. But as the units are assigned in the instruction with VLIW, you can't run code for one VLIW on another model with greater or fewer processing units as the instructions for that would have more or less slots in their instructions, although some greater ones might allow running code that uses a format which has fewer slots, unlike in a CISC or RISC where the code can automatically use additional processing units, the VLIW code can't use the extra processing units without being recomplied specifically for the processor.

That limitation with VLIW is what prompted Explicit Data Graph Execution (EDGE).

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