Question

The Intel i486 has 8 KB of L1 cache. The Intel Nehalem has 32 KB L1 instruction cache and 32 KB L1 data cache per core.

The amount of L1 cache hasn't increased at nearly the rate the clockrate has increased.

Why not?

Answer 1

30K of Wikipedia text isn't as helpful as an explanation of why too large of a cache is less optimal. When the cache gets too large the latency to find an item in the cache (factoring in cache misses) begins to approach the latency of looking up the item in main memory. I don't know what proportions CPU designers aim for, but I would think it is something analogous to the 80-20 guideline: You'd like to find your most common data in the cache 80% of the time, and the other 20% of the time you'll have to go to main memory to find it. (or whatever the CPU designers intended proportions may be.)

EDIT: I'm sure it's nowhere near 80%/20%, so substitute X and 1-X. :)

Answer 2

I believe it can be summed up simply by stating that the bigger the cache, the slower the access will be. So a larger cache simply doesn't help as a cache is designed to reduce slow bus communication to RAM.

Since the speed of the processor has been increasing rapidly, the same-sized cache must perform faster and faster in order to keep up with it. So the caches may be significantly better (in terms of speed) but not in terms of storage.

(I'm a software guy so hopefully this isn't woefully wrong)

Answer 3

From L1 cache:

The Level 1 cache, or primary cache, is on the CPU and is used for temporary storage of instructions and data organised in blocks of 32 bytes. Primary cache is the fastest form of storage. Because it's built in to the chip with a zero wait-state (delay) interface to the processor's execution unit, it is limited in size.

SRAM uses two transistors per bit and can hold data without external assistance, for as long as power is supplied to the circuit. This is contrasted to dynamic RAM (DRAM), which must be refreshed many times per second in order to hold its data contents.

Intel's P55 MMX processor, launched at the start of 1997, was noteworthy for the increase in size of its Level 1 cache to 32KB. The AMD K6 and Cyrix M2 chips launched later that year upped the ante further by providing Level 1 caches of 64KB. 64Kb has remained the standard L1 cache size, though various multiple-core processors may utilise it differently.