RISC, when honestly stated, stands for "Reduced Instruction Set Complexity" -- The number of instruction is not necessarily reduced, but each instruction is simpler, in terms of the machine cycles required to execute it and in terms of the number of gates (or microcode store) devoted to implementing it.
The theory (which is at least partially realized) is that by reducing the amount of control logic, more chip space is available for registers and data path. Hence RISC machines typically have 2-4 times as many registers as their CISC counterparts.
This leaves the compiler to do the work of that omitted control logic, including "scheduling" operations (sequencing them) so that, say, you don't do two adds back-to-back but do an add then a shift (and on different registers) so both the adder and the shifter are optimally utilized. And the compiler must also manage the register set, to optimize movement into and out of registers, minimizing storage accesses. Plus the compiler must know how to best utilize the odd instructions (such as a "shift left one and mask with literal"), as these usually have some (perhaps strange) scenario where they are relatively powerful.
As a result, the instructions generated by a good RISC compiler are virtually impossible to decipher. Even if you know the instruction set well, figuring out that some value from half an hour ago is still in register 12 is difficult at best, even if it weren't for the convoluted shift and mask operations occurring all the time.
(For those who apparently don't believe I know what I'm talking about, I was first involved with on RISC with the IBM 801, in the early 70s, and I was on a first-name basis with George Radin and Marty Hopkins.)