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Reduced Instruction Set Architecture (RISC) aims to reduce the number of instructions thereby improving performance . The only downside to this approach is that the compilers have to be "smarter" .

What does my lecturer mean when she said "compilers have to be smarter" and why is this so

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RISC, when honestly stated, stands for "Reduced Instruction Set Complexity" -- The number of instruction is not necessarily reduced, but each instruction is simpler, in terms of the machine cycles required to execute it and in terms of the number of gates (or microcode store) devoted to implementing it.

The theory (which is at least partially realized) is that by reducing the amount of control logic, more chip space is available for registers and data path. Hence RISC machines typically have 2-4 times as many registers as their CISC counterparts.

This leaves the compiler to do the work of that omitted control logic, including "scheduling" operations (sequencing them) so that, say, you don't do two adds back-to-back but do an add then a shift (and on different registers) so both the adder and the shifter are optimally utilized. And the compiler must also manage the register set, to optimize movement into and out of registers, minimizing storage accesses. Plus the compiler must know how to best utilize the odd instructions (such as a "shift left one and mask with literal"), as these usually have some (perhaps strange) scenario where they are relatively powerful.

As a result, the instructions generated by a good RISC compiler are virtually impossible to decipher. Even if you know the instruction set well, figuring out that some value from half an hour ago is still in register 12 is difficult at best, even if it weren't for the convoluted shift and mask operations occurring all the time.

(For those who apparently don't believe I know what I'm talking about, I was first involved with on RISC with the IBM 801, in the early 70s, and I was on a first-name basis with George Radin and Marty Hopkins.)

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How old are you? – Pacerier May 20 '15 at 7:47
@Pacerier - As my profile says -- older than dirt. – Daniel R Hicks May 20 '15 at 11:54
I don't believe you're older than me. – Pacerier May 24 '15 at 13:57
@Pacerier - Well, if you were a classmate of Grace Hopper you've got me beat. – Daniel R Hicks May 24 '15 at 17:09

Since there are less instructions in a RISC CPU, there's less of a chance that a single high-level statement will translate nicely to a single machine language opcode.

A synonym for RISC CPU is "load-store architecture." Basically, it means that RISC instructions that actually do work generally work on registers only. If you want to work on values stored in RAM, you have to issue explicit LOAD instructions, whereas CISC CPU's like x86 have instructions that automatically do that. RISC CPU's have historically had more registers than x86 - and good code will manage the available registers well to avoid unecessary memory accesses, meaning a compiler needs to take that into account.

Another thing is that RISC CPU's typically only provide the minimum "infrastructure" needed for linkage.

For example, x86 CPU's have a notion of a "stack", where you can push values, and later "pop" them off (there are PUSH and POP instructions). There is also a CALL instruction - it will push the current instruction pointer on the stack and then jump to the destination address - typically a subroutine or function. A RET instruction can then be later issued to pop that saved instruction pointer off and resume from the original function. Nesting subroutines is convenient, and you can use PUSH and POP to put parameters for subroutines easily.

On a MIPS, for example, all you have is a jal for "Jump and Link" - it puts the current instruction pointer in a register and then jumps to that address. If you want to do something like a stack or the x86 CALL instruction, you have to do that manually. This requires more intelligence from the compiler.

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CISC (Complex Instruction Set Computing) Processors have a larger range of insturctions available to them than RISC (Reduced Instruction Set Computing) Processors.

An example of multiplication in CISC would be: MUL 1:3, 4:2 (Multiply 1:3 and 2:4). This command would load the value in position 1:3 in its register, load the value in 4:2, multiple them together and store it back to 1:3

RISC CPUs could have to:

  • LOAD A, 1:3
  • LOAD B, 4:2
  • PROD A, B
  • STORE 1:3, A

...4 RISC operations to 1 CISC Operation.

Because RISC requires more operations to even do the simplest multiplication calculation - imagine how much more work is required for things like a video rendering or gaming?

With this in mind - the compilers that build the software from the code entered by a programmer need to be "smarter" so that they know how to simplify complex pieces fo code and complex commands for RISC Architecture.

Hope this makes sense For further reading, it may be worth looking at:

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Yeah, that's what the PR would have you believe. But actually in many cases the (so-called) RISC instruction set is larger than the more-or-less equivalent CISC set. The distinction between the two is that the RISC CPU is not microprogrammed and hence has more primitive instructions. Often a sequence of instructions must be used to accomplish what would be one CISC instruction. Many RISC designs do not support integer multiply/divide, eg. – Daniel R Hicks Mar 7 '14 at 13:09

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