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When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly interested in RISC architectures for the simplicity, since CISC may contain complex microcode.

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I think your confused by how instructions work. An instruction can't take multiple clock cycles. Now a series of instructions that make up a method is something else entirely. As for tracking the progress that's what the cache is for – Ramhound Mar 9 '14 at 1:13
Many RISC systems doesn't have multi-cycles instructions. Not having to keep track of multi-cycles instructions are part of what makes them much simpler than CISC. – Lie Ryan Mar 9 '14 at 1:16
Today's machines (even single core) are normally executing several instructions at once. You should look for resources on computer architecture (there sure are lots of lecture notes and other resources of the net). – vonbrand Mar 9 '14 at 2:47
@Ramhound Of course an instruction can take multiple clock cycles. Multiplies typically take longer than adds, for example. – David Schwartz Mar 9 '14 at 2:54
if one looks at pictures in old textbooks, the "program counter" gets incremented. you can read about the 'program counter' 'memory address register' memory buffer/data register'. address bus, data bus, control bus or control lines. – barlop Mar 9 '15 at 16:49
up vote 1 down vote accepted

Typically, for simple CPUs that are not superscalar and don't have sophisticated pre-fetch or pipeline logic, this is done by an actual circuit connection. When an instruction is retired, a wire from the retire logic to the fetch unit triggers the fetching of the next instruction.

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What you are asking can be found by googling for "Processor timing diagram":

Inside the timing diagram you can see when instructions is put on the bus, and when it is completed it can triggered the next instruction to be fetched etc.

Yes, different instructions have different number of clocks cycles - eg, those XMM instructions from Intel architecture are going to take much longer than a simple XOR operation. Moreover, due to caching, and pipelining, the SAME instructions may even have different overall latencies.

Since you asked for RISC then perhaps you should read the ARM processor timing diagram:

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