When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly interested in RISC architectures for the simplicity, since CISC may contain complex microcode.
Typically, for simple CPUs that are not superscalar and don't have sophisticated pre-fetch or pipeline logic, this is done by an actual circuit connection. When an instruction is retired, a wire from the retire logic to the fetch unit triggers the fetching of the next instruction.
What you are asking can be found by googling for "Processor timing diagram":
Inside the timing diagram you can see when instructions is put on the bus, and when it is completed it can triggered the next instruction to be fetched etc.
Yes, different instructions have different number of clocks cycles - eg, those XMM instructions from Intel architecture are going to take much longer than a simple XOR operation. Moreover, due to caching, and pipelining, the SAME instructions may even have different overall latencies.
Since you asked for RISC then perhaps you should read the ARM processor timing diagram: