So the manufacturing processes for CPUs goes down every second generation (for Intel), but I couldn't get the math right. Let's say we have a CPU with a size of 10mm*10mm, that makes a die area of 100mm^2. And let's shrink the manufacturing process let's say from 100nm to 90nm, so a 10% reduction. Would the same chip with the new process be of dimension 9mm*9mm? That would mean the reduction is linear in length, and therefore quadratic in the die size, because the new die size is 0.9^2 * 100mm^2.
The reason I'm asking is because I was doing some rough calculations based on the Sandy / Ivy Bridge Shrink and die sizes, and couldn't get a good answer. Sandy Bridge was 32nm, Ivy was 22nm, that's a factor of ~1.45. According to Wikipedia the die sizes of the two most comparable models (4 cores, same L3 cache) are 216mm^2 and 160mm^2. That makes a factor of 1.35 while it should be over 2 because 1.45^2=2.10. Or does the production process affect the die size linear, not the width/length? But then: why? And the other shrinks don't really add up either. Or is the real problem the architectural changes besides the production process? i.e. more transistors. I'm confused.