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I have a host device consisting of an Intel CPU and a PCIe switch; and I also have an adapter card which itself has some CPU, some PCIe end-point peripherals, and a PCIe switch. Normally only the adapter card's CPU uses the end points and it sends data to the Intel by a means not depicted below, but I'd like to change that.

Is there any PCIe switch configuration which would allow both CPUs to enumerate the End-Point devices such that I could move some, but not all, functions off the adapter card's CPU and onto the Intel CPU?

If the adapter card's switch’s connection to the host was configured as an NTB, would it appear to the Intel CPU as a single device? If so, who is responsible for configuring the address map?

diagram

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  • Just thinking out loud. Maybe if both endpoints supported SR-IOV you might be able to do some custom software work to get it to work not sure there. Can the CPU function as a device (endpoint)? Maybe then you could hang everyone off of the Intel CPU. Then your local CPU could still access your endpoints through PCIe memory space.
    – Some Hardware Guy
    Oct 28, 2014 at 14:45
  • The endpoints do support SRIOV, they are Xilinx PCIe Gen 3 Cores on FPGAs. I don’t really know what SRIOV is, but it looks to me like a method to make one end point appear to be multiple end points. I know you were just thinking out loud, but perhaps you could expand on that a bit? Your second comment about using the CPU as an endpoint is very intriguing. The CPU on the adapter is a Zynq, which apparently supports being an RC or an EP. I'll have to research this a bit since I'm not sure what affect having that CPU be an end point will have on other parts of the system.
    – Jay
    Oct 28, 2014 at 17:11
  • I thought about this a bit more. While changing the adapter's CPU to EP mode would allow the adapters PCIe switch to be confugred without NTB, thus allowing enumeration of the end points from the host CPU, I believe it might be the same amount of total work as allowing the host CPU to directly enumerate the end points and placing the adapter CPU on an NTB port instead. I may be asking for the impossible... a way to enumerate the same end points from two RCs...
    – Jay
    Oct 28, 2014 at 18:06
  • SR-IOV is "Single Root I/O Virtualization" If anything your EPs would need to support MR-IOV "Multi Root I/O Virtualization".
    – Tim
    Nov 10, 2014 at 17:33

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