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Can someone tell me what level and edge triggered interrupts are? Or give me a link to an article with a simple explanation?

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up vote 4 down vote accepted

So here's a signal line in a quiescent state (special ASCII oscilloscope reenactment):


That represents one copper wire carrying one voltage with no variations over some period of time. In digital electronics, that voltage is either 0v or 5v, a.k.a. 0 (zero) or 1 (one).

Let's say that wire is normally kept at 0v (zero volts). If I send a pulse down that line, that means I apply a higher voltage, say, 5v (five volts). On an oscilloscope, the transition from low to high looks like this. That part where the transition happens is an edge.

                                 -------------------------- +5v
0v -------------------------------


So in edge-triggered interrupts, there's a wire connecting the CPU and some device that's normally kept, say, at 0v. When the device wants to get the CPU's attention, it sends an interrupt: it puts power to that wire. The CPU detects the new high voltage on the wire and triggers an interrupt handler to deal with it. Then the device stops putting power on the wire, and the voltage heads back down to 0v.

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Two seconds with a search engine pointed me at Wikipedia:

An edge-triggered interrupt is a class of interrupts that are signalled by a level transition on the interrupt line, either a falling edge (1 to 0) or a rising edge (0 to 1). A device wishing to signal an interrupt drives a pulse onto the line and then releases the line to its quiescent state.

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