If I have a system with a single level paging memory manager ( without TLB).. How much time is needed for this system to access the memory ? I've been reading twice as long without the memory manager .. Is this true ? If not how long without a memory manager ( give or take ) would it be.
If you're using an MMU, each memory access has to look up the mapping from virtual to physical address, which incurs an overhead of one memory access per level of the page table hierarchy. In practice, most modern MMUs use about three levels.
This data structure has a table broken into several levels. The first level corresponds to the high order bits of the virtual address, the next level to the next few bits and so on. Mapping from a virtual address to a physical one involves looking up the relevant bits of the virtual address at each level of the page table. The leaf nodes have a page number in physical memory and some flags marking protection, dirty and whether the page is physically present in memory.
On some architectures (such as SPARC64 and PPC) a data structure called an 'inverted page table' is used as standard hierarchical page tables can be infeasibly large or deep on such a large address space. Inverted page tables have one entry for each virtual page in the process address space and use hashing to look up the physical page data. This is nominally O(1) but can result in collisions driving extra memory accesses.
As one might surmise this process is quite slow, especially when the page table data isn't in cache and incurs cache miss costs (which can take hundreds of cycles). Fortunately, MMU accesses typically demonstrate very high locality of reference, so they are amenable to caching. The caching mechanism for logical-physical page mapping is called a Translation Lookaside Buffer (TLB).
The Translation Lookaside Buffer caches the mappings, reducing the incidence of having to walk the page table data structure. Generally, only a fairly small TLB is necesary to get good efficiency, although it is quite easy to write code that accesses memory in patterns that thrash the TLB.
Without an MMU the memory access does not have to do any indirection, so it is as long as a memory access on the system, with the proviso that optimisation of cache access patterns can still have a large effect on performance.
Unfortunately you need to give more exact info for an answer but I'll try:
It depends on how the paging memory manager works, what the settings are, and what system components it is being used with. The "twice as long" is probably a good ballpark figure, but you really can only tell by testing it yourself with and without the memory manager.