Computer architecture refers to various aspects of computer system designs which can affect compatibility, performance, and interfacing. Some issues related to computer architecture can be processor word size, memory bus size, or protocol implementation.

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How To Alphabetically Organize Zip Files With Folders In Windows 8

In Windows 8, when I have a zip file in a folder of folders, it doesn't sort by name. The folder ends up looking something like this: gymnastics (folder) juggling (folder) unicycling (folder) ...
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What converts binary code/machine code to electrical signals and how? [closed]

I went through lots of blogs and posts but could not exactly figure out how the machine code is converted to electrical signals? Any software program is compiled to machine code which is nothing but ...
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3k views

What is the actual speed of SATA 3?

Google says it is running at 6Gb/s. The throughput is at 600MB/s. 600MB/s equals 4.8Gb/s. Does this mean that the bandwidth is 6Gb/s but the actual throughput is 4.8Gb/s ?
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21 views

Is there a difference between i/o port and physical port?

AFAIK, the following definitions apply: i/o ports are memory adresses used as an interface to communicate with external devices e.g. a printer. A physical port (i.e. connector) is the physical ...
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What happens if the associativity level is greater than the cache size?

I am working on a computer organization caching problem The Problem: What happens if the associativity level is greater than the cache size? I know that associativity level is how many blocks are ...
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Will this address result in a cache hit or miss for these cache mapping functions?

The Problem: A CPU produces the following sequence of read addresses in hex.    Suppose the cache is empty to begin with and assuming an LRU replacement, determine whether each address ...
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82 views

How many bits are in the address field for a directly mapped cache?

Here is the problem I am working on: The Problem: " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 ...
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54 views

How many words can be in the address space?

Here is the problem I am working on The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address ...
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2answers
79 views

What does “address resolution at the byte level” mean?

Here is the problem I am working on The Problem :A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address ...
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2answers
84 views

If a 32 bit CPU has a 64bit bus system, is it 64 bit or 32 bit?

Let's say the internal registers of a CPU are 32 bits wide. But the CPU has a 64 bit system bus and the two separate pipelines are receiving information simultaneously, is it considered a 32bit ...
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46 views

How does a CPU decide which transistors to use? [closed]

Perhaps I'm not thinking about this correctly, but when you give the CPU a command such as Multiply Registers (MR) R2,R4 how does it decide which logic gates it will use, is it just the first gates ...
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82 views

What factors other than clock speed influence the performance of a CPU? [duplicate]

Having seen various people test powerful emulators on their computers, I have come to surprise hearing about how one CPU can have triple the clock speed but still have worse single-threaded ...
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26 views

What is this logic component?

This is from http://www.cis.upenn.edu/~milom/cse240-Fall05/handouts/Ch05.pdf , slide 9. From this diagram, I recognize 0001 as the opcode or ADD. I recognize 011, or 3, as the source register and ...
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2answers
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What exactly is present in CMOS when system is turned on for the first time?

Also, how does the CMOS get all the hardware information/parameters and store them?  Does the BIOS write them into the CMOS or some other hardware? BIOS has the facility to do POST. Is POST somehow ...
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Why is it not recommended to shut down a computer “brutally” (power switch)? [duplicate]

It is now in the general knowledge that one should not shut down a computer using its power switch. But why is that exactly? Is it a myth that stuck from past architectures? Is it solely to prevent ...
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2answers
187 views

Is disk read/write speed affected by processor architecture? [closed]

I am not sure what effect if any a 32 bit vs 64 bit architecture processor has on disk read/write speed. I believe that a 64 bit processor can address more main memory than 32 bit processor without ...
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1answer
544 views

Average time to read a single sector (disk)

If there is a magnetic disk as following: Average seek time: 12 ms Rotation rate: 3600 RPM Transfer rate: 3.5 MB/second Number of sectors per track: 64 Sector size: 512 bytes Controller ...
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5answers
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Why a disk drive could not be connected (physically) to 2+ computers?

A friend of mine if a disk drive could be connected to more than one computer and I jumped directly to the "no" answer, but I realized that pretty much any inconvenient I could think of would be easy ...
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98 views

Why do uname -p and uname -m and arch output different architectures?

On mountain lion (late 2010) $ uname -p i386 $ uname -m x86_64 $ arch i386 So i368 (32 bit) is my processor architecture, and x86_64 (64 bit) is my machine hardware name according to the uname man ...
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822 views

understanding CPU,RAM,and Hard Disk Drive [duplicate]

I'm currently reading about how the computer works, specifically how the CPU, RAM, hard disk drive work together simultaneously. According to what I have read, the CPU uses what is called a control ...
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1answer
21 views

What is the state of the art in hardware for data error correction?

A decade (or more) ago when shopping for RAM one often had the option of specifying "server-grade" memory with an extra Error Correction Code (ECC). I haven't seen that as an explicit option in ...
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31 views

Why is cache leakage power consumption higher than other hardware units?

Is it correct that caches (SRAM cells) have higher leakage power compared to other hardware units with the same area such as ALU? And if so, why is the case?
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369 views

Is Modern Computers based on Von Neumann Model?

I read it on the Foundation of Computer Science(by Behrouz A. Forouzan) textbook that a Von Neumann model's program must execute sequentially and the modern computer execute code in the order that's ...
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50 views

Recovery of data from hard disk

Let's assume I have consumed 100% space of HDD with 3 movies (A,B,C) Now i have deleted A,B,C and filled 100% space of HDD with movies (D,E,F) can i recover the files A,B,C from the hard-disk? PS: ...
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225 views

32-bit to 64-bit skipping 48-bit?

Computer architecture upgraded from 16-bit to 32-bit to 64-bit. What was the logic for skipping 48-bit? What reasoning was used to upgrade to 64-bit and not some other exponent? The following tables ...
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331 views

x86 i386 i686 amd64 i5 i7 archtecture processor confusion

I noticed those items x86, i386, i686, amd64, i5, i7, archtecture, processor from the web, from my own notebook, from book readings. But I am really confused by those terminologies. I try my best ...
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Formatting a PC without admin rights

I was at a flea market the other day and bought a computer. However, the computer is locked and I can't login to it. Is there a way to format the computer and install Linux on it? It seems like the ...
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44 views

Calculating RPM of the disk drive

Well I have a question about RPM of the disk drive. I've seen an example where: seek time of the HD: 5ms track size: 5MB If an application wants to read 1MB from the disk with a maximum time of 20ms ...
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1answer
51 views

What architecture to choose with 2 GB of RAM in the computer [closed]

I have 2 GB RAM in my laptop. I want to install Window 7 Ultimate but I don't know which architecture to choose - 32 bit or 64 bit.
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1answer
136 views

Difference between “network RAM” and “distributed shared memory” (DSM)

What is the difference between "network RAM" and "distributed shared memory" (DSM)? Basically, I know that both of them provide a shared storage on RAM among all the systems in a cluster. So, what is ...
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1answer
329 views

Difference between “system-on-chip” and “CPU”

Very confused, in some websites, they have this line: iPhone 5s CPU: Apple A7 other websites saying that: iPhone 5s System-on-chip: Apple 7 CPU: 1.3 GHz 64bit dual core other sources saying ...
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187 views

why are RAM chips independent of whether my system is a 32bit system or 64 bit system?

I was recently out to buy a 4 GB RAM chip for my laptop, and all they asked me was whether I wanted DDR-3? When I specified that I had a 64 bit system, they said that it's not important, my question ...
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652 views

How mouse button re-mappings work?

I installed my new mouse (Anker 2000 DPI Wireless) and then the driver which installs a program named '5-button mouse' that allows me to remap what each button does, standard stuff and everything ...
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Is parallelism in computer science always directly tied to the number of processor cores?

Specific to the Java programming language, would it be accurate to say that two threads can be concurrent, but can only truly be run in parallel if there are two or more cores?
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How do modern smartphones compare to Apollo mission computers? [closed]

I saw an article some time ago that compared smartphones to the computers that had put mankind on the moon. I can't remember the exact comparison and I can't find an accurate comparison online, as ...
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1answer
794 views

How BIOS extensions (option ROMs) work?

How do BIOS extensions (option ROMs) work? I understand that an installed device may have it's own BIOS that adds features to the system but I'm not sure of how they are set up. I keep reading the ...
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1answer
581 views

PCI BAR memory addresses

Quick question, I was reading the OSDev Wiki page regarding PCI and it says the following - Base address Registers (or BARs) can be used to hold memory addresses used by the device, or offsets for ...
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1answer
2k views

Whats the difference between physical and virtual cache?

I am having trouble understanding what virtual cache actually is. I understand virtual memory. If the CPU wants to access memory, as far as I understand, it sends a virtual address to the MMU which, ...
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1answer
265 views

Why can't PCIe devices share lanes?

On older chip-sets it was not possible to have a dedicated graphics card in the PEG slot and have the Integrated Graphics Device (IGD) enabled at the same time. After looking online I found this was ...
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1answer
349 views

How are reserved and ACPI NVS memory sizes counted?

My PC has 8GB of memory installed and is running Win 7 64-bit. I ran a tool named fwmemmap that shows the firmware memory map for the system but it's showing around 60MB more than is physically ...
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151 views

where and How the computer/mobile phone time and date stored

i tried something, i noted down the current time within my laptop(dell.. win 7) it was 12.15 PM 5 April 2014, and i did the same with my mobile phone(samsung galaxy s2, andriod jelly bean) it was ...
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1answer
62 views

Harvard Architecture : How does it improve speed?

I don't understand the difference between Von Neumann and Harvard architectures. Let's say you have these two instructions : MOV ax, [address2] MOV bx, ax In Harvard architecture, the processor ...
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29 views

How are graphics produced on the screen?

I have been trying to get a complete answer to this for a long time and I know it is complex. For example lets say we wanted to produce the character 'H' on the screen. H is 72 in ascii or 48 in Hex ...
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2answers
1k views

What is the difference between primary and secondary bootloader?

What is the difference between primary and secondary bootloader? Does primary and secondary refer to the two parts of the bootloader or two stages of the bootloader? I am confused.
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2answers
62 views

How does an instruction in a CPU report that is has finished?

When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly ...
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3answers
483 views

Why do compilers have to be “smarter” for RISC instruction set architecture

Reduced Instruction Set Architecture (RISC) aims to reduce the number of instructions thereby improving performance . The only downside to this approach is that the compilers have to be "smarter" . ...
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How does fabrication process and compiler quality affect CPU performance

I was reading up on my lectures and one of the slides listed down the factors affecting CPU performance , I cant understand how does fabrication process and compiler quality affect CPU performance
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349 views

What is the difference between the terms “memory”, “main memory”, “RAM”, “Memory bank” and “Memory Module”

What is the difference in the followoing words? They seem to all be interchangable. Memory, Main memory, RAM, Memory bank, Memory Module. Correct me if I'm wrong but my understanding is memory is a ...
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1answer
294 views

Why is this memory range on the PCI bus?

Why is the following memory address range on the PCI bus? The image is from my Netbook that uses shared video memory with no dedicated video memory so I am unsure as to why the VGA memory range ...
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ReadyBoost : How a Software Component Helps Boost the System Performance by Exploiting Flash Memory as a Cache?

One of the nice feature of windows 7 for low memory system is ReadyBoost, a software component that uses flash memory as a cache to actually speed up the the performance(Ref-Wikipedia). But If we ...