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1answer
32 views

What does “book” mean in the output of 'lscpu -p'?

On Linux, the lscpu -p command outputs lots of information about the CPU architecture. One of the columns is the "book number". What does "book" mean in this context? EDIT: the documentation of lscpu ...
0
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0answers
25 views

Why is cache leakage power consumption higher than other hardware units?

Is it correct that caches (SRAM cells) have higher leakage power compared to other hardware units with the same area such as ALU? And if so, why is the case?
0
votes
2answers
77 views

Would Like to Upgrade CPU of hp pavilion touchsmart 11z-e000 Notebook

I recently bought a HP TouchSmart 11Z-e000 Laptop but I am not happy with performae. It is using AMD A4 CPU with 4 GB RAM. I think the RAM is enough. Culprit here is CPU for the slow performance. I ...
5
votes
2answers
180 views

32-bit to 64-bit skipping 48-bit?

Computer architecture upgraded from 16-bit to 32-bit to 64-bit. What was the logic for skipping 48-bit? What reasoning was used to upgrade to 64-bit and not some other exponent? The following tables ...
92
votes
13answers
11k views

Why doesn't “add more cores” face the same physical limitations as “make the CPU faster”?

In 2014, I hear a lot of programming languages touted for their concurrency features. Concurrency is said to be crucial for performance gains. In making this statement, many people point back to a ...
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votes
3answers
275 views

Defining 32-bit or 64-bit processor requirements [duplicate]

My knowledge of computer hardware is fairly extensive, however it is apparent that this is not the case when considering types of operating systems. I've gone by the rule of thumb for years that if a ...
-3
votes
2answers
148 views

What is the on-chip network topology of an Intel Core i7 (or i3 or i5) processor?

What is the topology of the interconnection network within an Intel core i7 ,i3 or i5 processor? Is it using a: Crossbar Ring Hypercube Mesh Butterfly or what ?
0
votes
0answers
26 views

How are graphics produced on the screen?

I have been trying to get a complete answer to this for a long time and I know it is complex. For example lets say we wanted to produce the character 'H' on the screen. H is 72 in ascii or 48 in Hex ...
1
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0answers
269 views

How to determine control/data/address bus width

I am hoping you guys can help. I need to know how to calculate the control bus, address bus, and data bus width of a hypothetical CPU. A computer is word addressable with a 64 bit word size and ...
0
votes
1answer
37 views

How does an instruction in a CPU report that is has finished?

When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly ...
15
votes
2answers
361 views

Are 64-bit processors “faster” than 32-bit ones, simply because they are 64-bits? [duplicate]

I have pondered that some say "32-bit is old news" because you are limited in RAM without cutting around, such as with PAE. Assuming first that the following factors weigh in on the processor's speed ...
1
vote
1answer
106 views

Confusing info from /proc/cpuinfo: CPU Frequency:

I ran a 'cat /proc/cpuinfo' on a node I'm using and obtained the following: processor : 13 vendor_id : GenuineIntel cpu family : 6 model : 62 model ...
7
votes
1answer
101 views

How do general binaries take advantage from new instructionsets on new CPUs

With every release of a new processor, there are changes to the instructionset the processor supports. For example, Haswell has Advanced Vector Extensions. However, when I run a program on a PC with a ...
2
votes
2answers
69 views

CISC and VLIW, and instruction and opcode

From http://en.wikipedia.org/wiki/Instruction_set CISC processors include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many ...
3
votes
2answers
112 views

Do emulators parse binary code within files?

I have seen some emulators that claim they execute, and even though they do, their source code shows they don't directly parse every 1 and 0 to determine an instruction. My question is, if the ...
2
votes
2answers
174 views

Why CPU emulation is slow [closed]

Different CPU (IA-32, ARM9 etc.) operations should be equivalent in their nature (move, read, write data etc.). It shouldn't be that painful for different CPUs to emulate each other. But seems like ...
3
votes
1answer
1k views

Why do we need multiple levels of cache memory?

In general a cache memory is useful because the speed of the processor is higher than the speed of the ram (they are both increasing in speed but the difference still remains). So reducing the number ...
3
votes
3answers
722 views

What's the difference between a hardware register and a memory-mapped register?

This has been puzzling, so I'll lay it all out here. Apparently, through MMIO, you can access external devices using a certain memory-mapped address, which would then be re-routed to that device ...
1
vote
1answer
119 views

When modern computers boot, what initial setup of RAM do they execute, and how does it exactly work?

I know the title reeks of confusion, and some of you might assume I am just wondering about how the computer boots in general, but I'm not. But I'll sort this out for you people now: 1.Onboard ...
1
vote
1answer
109 views

Which enhanced instruction set does an application use?

Is there any reliable and easy way to establish whether an exe or dll uses a particular enhanced instruction set (e.g. SSE4.1)? Disassembling it with ndiasm seems to produce a listing which you could ...
2
votes
1answer
248 views

How interrupts and privilege levels work?

I'm trying to get a better understanding of how interrupts work (both hardware and software) and the privileges that go with them. If we use the NIC as an example. When the OS creates the IDT, does ...
5
votes
1answer
4k views

Why SRAM is faster than DRAM?

In modern multi-core processors, the processor caches (L1,L2 and L3) are made up of SRAM with decreasing speeds(L2 caches are higher speed SRAM than L3 caches which is a cost trade-off). The main ...
5
votes
1answer
1k views

Is it possible for an x86 processor to match an ARM processor in terms of performance per watt?

From my personal experience with my tablet, and from the benchmarks and articles I've read, it always seems ARM processors, as seen in virtually all mobile devices, deliver incredible performance for ...
4
votes
3answers
306 views

Does a hotter processor run faster?

I heard from a physicist that when silicon gets hotter it can conduct more electricity through it. He said: "Silicon is going to have a pretty good structure, it's going to have higher melting ...
0
votes
2answers
653 views

Using 32bit application in 64bit

I am using windows 32 bit VLC media player in 64 bit pc. It is working fine. but my question is that won't it allocate memory according to 32 bit structure? That means though i have 64 bit PC, i ...
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votes
2answers
53 views

Will this combination of hardware work together? [closed]

I'm assembling a system with Motherboard: Intel DH61HO Processor: Intel Core i3 2105 Ram: Corsair DDR3 4GB DDR3-1333 Hard drive: ST500DM002 (500 GB, 7200 RPM) Is this combination compatible, or am ...
53
votes
9answers
9k views

Why have CPU manufacturers stopped increasing the clock speeds of their processors? [closed]

I have read that manufacturers stopped concentrating on higher clock speeds and are now working on other things to improve performance. With an old Desktop machine with Intel® Xeon® Processor E3110 ...
3
votes
1answer
2k views

Confusion with terms -> FSB, QPI, HT, DMI, UMI

I'm a bit confused about some terms used by CPU manufacturers. I know that FSB is a bus that connect the CPU to the Northbridge and that QPI (Intel) and HT (AMD) replaced this technology. The new ...
0
votes
1answer
81 views

x86 OS vs x86_64 OS and battery for laptop with an intel i5 [closed]

I recently purchased a new laptop with an Intel i5 and 6 Gigs memory for general usage. I'll have the time to install it this weekend and I'm wondering whether installing an x86 instead of an x86_64 ...
0
votes
1answer
3k views

How many registers does Intel® Core™ i7-3770T Processor have?

I've been looking at this website: http://ark.intel.com/products/65525/Intel-Core-i7-3770T-Processor-8M-Cache-up-to-3_70-GHz But I can't figure out the number of registers.
0
votes
5answers
137 views

Are there CPUs with true shared memory? [closed]

I work on parallel algorithms and want to validate certain theoretic claims by runtime experiments. As it turns out, most (?) modern multicore CPUs use NUMA which inherently breaks many models to the ...
4
votes
3answers
654 views

where does Kernel reside on a multi-core system

Suppose I have a multi-core system, say 4 cores, and in this I pin 3 user process to a 3 CPU's. In such a case, where will the kernel reside? Suppose one of the user process make a system call, or ...
16
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2answers
743 views

Why are newer generations of processors faster at the same clock speed?

How come, for example, a 2.66 GHz dual-core i5 will be faster than a 2.66 GHz Core 2 Duo (also dual-core)? Is this because of newer instructions that can process information in less clock cycles? ...
1
vote
1answer
113 views

When a thread is created, how is the initial context determined? [closed]

How is a thread's initial context (registers state) determined on thread creation? For example: Current thread context eax=0x4, ebx=0x9000, ecx=0xfff, etc... Create a thread is called to begin ...
2
votes
2answers
69 views

Instruction assignment with multiple CPUs

Maybe this is a stupid question but I am trying to gain a better understanding of hardware inner workings... If a machine has two or more CPUs, which hardware component is actually responsible for ...
0
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2answers
3k views

CPU and Motherboard clock speeds

I have been doing some reading about CPU clock speeds and how CPU clock speeds are calculated. After reading several articles, I have come to the understanding that your CPU clock speed is determined ...
4
votes
4answers
4k views

How can I find a list of all SSE instructions? What happens if a CPU doesn't support SSE?

So I've been reading about how processors work. Now I'm on the instructions (SSE, SSE2, etc) stuff. (Which is pretty interesting). I have lot of questions (I've been reading this stuff on Wikipedia): ...
1
vote
0answers
813 views

Using UEFI to access CPU features which are locked in BIOS

I have Dell Latitude E6420 with SandyBridge i5-2520M and standard issue Dell BIOS (version A15). In certain situations computer produces annoying high-pitched noise (it is not loud but it is ...
0
votes
1answer
103 views

Requirements to change a 32-bit CPU with a 64-bit CPU [closed]

I want change my 32-bit Athlon with a 64-bit Phenom. Do I need to change my OS (32-bit Windows 7) as well?
0
votes
1answer
941 views

Is little-endian still faster on Intel processors or it does not matter if I parse big-endian on intel? [closed]

It used to be in past architectures. Is it still the case? I am reading from the network into byte buffers in Java. Basically, will read bytes on Intel using big-endian instead of little-endian ...
0
votes
1answer
518 views

Core i3 3220 for gaming [closed]

Since the Core i3 3220 has Hyper-Threading, will games like Battlefield 3 see and use the CPU as a virtual "quad core" rather than just 2 physical cores, so that AI and other features in the game run ...
0
votes
1answer
729 views

Direct Memory Access(DMA) controllers for intel

Does intel in it's current generation of processors provide any Direct Memory Access(DMA) controllers? If yes is it built into the chip? http://en.wikipedia.org/wiki/Direct_memory_access
3
votes
1answer
678 views

Understanding the nop byte(s)

Ok, so I was reading through the AMD64 manuels and knowing that nop is really an xchg eax, eax, I looked at the xchg and found something interesting, that it seems a byte can be encoded into the ...
2
votes
1answer
365 views

“nop; jmp short” vs. “jmp short; nop”

Ok, first let me get this straight: This is not about micro optimization. But, I know in bootloaders on the partition, a lot use the jmp short; nop coding. But it is to my understanding that the less ...
1
vote
2answers
220 views

Hardware. What is the difference between a port and a bank?

Especially, these days, the distinction between them is very confusing.. For example, NVidia's shared memory is 32-banked, so what they say is in one cycle, 32 data can come out at the same time... ...
3
votes
3answers
104 views

How to count the approximate number of Intel-compatible binaries/programs on a computer running OS X Lion, and time that count?

For an approximate count — and to get an idea of the time taken to count — I began with a multi-line command that could run in tcsh. I'm not a plumbing expert, so I invite answers that are better ...
5
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2answers
7k views

What`s the difference between Intel 64 and AMD64?

Can someone explain if there is any difference between the intel64 and amd64 architectures?
2
votes
1answer
2k views

VMWare on Intel i7-2600[S/K]: VM processor configuration for maximum performance

I have an Intel i7-2600K-processor, which has 4 cores but runs 8 thread because of Hyperthreading. I want to run a Ubuntu-VM with maximum performance under VMWare 8 (host system is Windows 7, and is ...
0
votes
1answer
143 views

i7-9XX vs i7-2XXX

It seems that the "older?" i7-9XX series processors are still quite common in new systems. Is there an advantage to these CPUs over the newer Sandy Bridge i7-2XXX series that is making them ...
11
votes
3answers
644 views

Will a new processor with slower clockspeed run legacy applications faster?

I'm using Linux and have an old P4 with about 3 GHz clock speed. Will a newer chip that had slower clock speed run my legacy applications faster or slower? I only use one application at a time, an ...