CPU Architecture refers to a collection of parameters about the design of CPU realized by its manufacturer, such as: its bit-ness or data bus width (16, 32, 64 bits) , Instruction Set (RISC, CISC,...), Memory Management, Threading, Virtualization support, etc

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binary not running on debian wheezy

I am compiling the following assembly program on debian wheezy, but it will not run giving me the error: -bash: ./power: cannot execute binary file Code .section data .section text .global _start ...
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operations process in a computer

Is it true that all high-level operations in a computer (say, copying, pasting, web surfing, running apps etc) are all finally converted to micro-operations (say, arithmetic, logical and shift) and ...
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Desirability of mixed architecture software [migrated]

Under what conditions can native code compiled for different architectures cooperate on the same operating system? When exactly is such mixing desirable? Can, say 32 bit code run within a ...
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Reading CPU model specific registers on linux

I am running Ubuntu 15.10 but testes it also on Debian. I have Intel i5-5675C processor. I am using msr-tools-1.3 to do it. I am able to read register 0x00001a2 with the following command: rdmsr ...
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1answer
34 views

Are cores in a CPU package always identical?

By identical, I mean having the same signature - family, model, stepping and brand string of the CPU (which essentially identifies a CPU model uniquely) If I'm not wrong, a CPU package goes into a ...
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2answers
62 views

Definition of a processor vs core (multiprocessor vs multicore)

After reading alot of links, it bothers me that there is so much overlap between simple definitions such as CPU, processor, core, etc. ...
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1answer
13 views

The main difference between Superscalar and Parallelism

In superscalar processing, more than one instruction is executed in parallel at each core, so how would that differ from parallel processing then? Thank you.
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17 views

Register allocation tables overwrite

Reading about the Xeon processor: the Xeon has two register allocation tables (RATs), each of which handles the mapping of one logical processor's eight architectural integer registers and eight ...
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19 views

What debian architecture do I need to download

I'm running a server with a i5 4440 CPU. Now according to the FAQ I thought I need to download the i386 version. Now I searched the internet and found some topics and some friends are telling me I ...
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21 views

Why does 'lshw' tell me “32 bits”?

I ran lshw from a LiveUSB, but I'm not entirely clear how to understand one part of the output. In the first part, it says width: 32 bits, but just a few lines down in the CPU details it says width: ...
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1answer
42 views

Conflicting answers regarding system compability + refurbished laptop + 32/64 bit

I've used SecurAble, system information and Regedit process to determine if I can install a 64-bit OS with my current configuration. SecurAble says it's expandable, but the other two say it's a x86 ...
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1answer
54 views

which one of these units is not located in the microprocessor?

I'm doing a test on general computer science and I think the answer sheet is wrong. The question is as follows: which one of these units is not located in the microprocessor? 1) Cache ...
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1answer
82 views

Does my processor support PAE?

I currently have the following system specifications: Windows 7 64-Bit Athlon 64 X2 (W) 4600+ 2.4 GHz 8GB of RAM 500 GB HD I'm planning on installing Xubuntu as a dual partition along side my ...
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3answers
280 views

Why multi core processors producing less heat

We are using multi core processors partially, because the waste heat of single core processors was to high to handle. (correct?) Now we are using multi core processors that create less heat and need ...
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1answer
258 views

CPU Upgrade: Pentium P6100 to i7 640M? [closed]

I have been using the Compaq CQ-62 358TU for a while now, and has treated me well, but needed a long sought after upgrade, (since I'm broke and would rather upgrade than buy a new computer). My plan ...
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2answers
83 views

Why did the system repair guy leave this two wires out like this?

Why system repair guy leave this two wires out like this? Will it cause problem in future?
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1answer
655 views

Does a CPU clock frequency vary on-demand?

On my machine (not a personal computer), I have 24 cores (2.4GHz) and I currently don't have any important process running. Right now, are all of my 24 cores running/vibrating at 2.4GHz or are some of ...
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0answers
58 views

Is there a pentium equivalent of any i-series processor?

I have a confusion with speed of processors and I want to know what makes say, i3 faster than pentium processor which pentium doesn't have? If we add more GHz to pentium will it be same as i3 in some ...
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2answers
86 views

RAM Limitation on 64 bit arch

I see that there are a lot of places mentioning 16 EB RAM limitation... However, isn't a modern register 64 bit? and if so, 2^64 should point to the number of registers possible and since they are ...
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2answers
296 views

Windows 8.1 32bit version upgrade to Windows 10 64bit version

I have a windows 8.1 32bit installation with 4GB of RAM and a x64 capable CPU. I've upgraded the RAM to 8GB and want to do the Windows 10 upgrade... as far as I'm aware the upgrade will do a like for ...
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2answers
198 views

Difference between a read and load

What is the major difference between read and load and write and store? I know it is a very basic question, but somehow I'm not able to get it.
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0answers
42 views

My Single-Threaded CPU-Overloading apps use a percent of a thread, graphs shows different results

I made very simple C++ app that contains an empty while(true); loop, I tried with both optimized (-O2) and without optimization, both gave the same result in Task Manager, I even tried same Java and ...
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2answers
156 views

Why is it said that 'The longer the pipeline, higher the processor clock rate' [duplicate]

I have been recently going through the hyper threading technology of Pentium 4. The number of pipeline stages is high in P4 and is said that it will increase the speed of clock rate. How is that ...
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304 views

How many bits are in the address field for a directly mapped cache?

Here is the problem I am working on: The Problem: " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 ...
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1answer
174 views

How many words can be in the address space?

Here is the problem I am working on The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address ...
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2answers
223 views

What does “address resolution at the byte level” mean?

Here is the problem I am working on The Problem :A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address ...
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1answer
4k views

Is the amount of NUMA nodes always equal to sockets?

I have used lscpu to check two servers configuration: [root@localhost ~]# lscpu Architecture: x86_64 ...... Core(s) per socket: 1 Socket(s): 1 NUMA node(s): 1 ...
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2answers
321 views

If a 32 bit CPU has a 64bit bus system, is it 64 bit or 32 bit?

Let's say the internal registers of a CPU are 32 bits wide. But the CPU has a 64 bit system bus and the two separate pipelines are receiving information simultaneously, is it considered a 32bit ...
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37 views

Why is Pentium 4 Prescott slow compared to Pentium M? [duplicate]

I was benchmarking if it is worth to put loop inside a callback function so I tested fourth order Runge-Kutta of on y'=y in C++, all with gcc 5.1 on Ubuntu with compilation command g++ -std=c++11 -O3 ...
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65 views

Do virtual machines not allow all host CPU extensions?

For convenience's sake I'm trying to run an otherwise "regular" installation of Gentoo Linux as a guest inside VirtualBox on a Windows 7 host. I bootstrapped the installation by using VirtualBox, ...
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2answers
89 views

How does a CPU decide which transistors to use? [closed]

Perhaps I'm not thinking about this correctly, but when you give the CPU a command such as Multiply Registers (MR) R2,R4 how does it decide which logic gates it will use, is it just the first gates ...
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1answer
81 views

Where is the CPUID string located in the CPU?

I'm a newbie to CPU architectures and design, I came up with the following question: Where is the CPUID string (like "GenuineIntel") stored? Is it hard-coded in the microcode ROM? Or is CPUID a ...
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1answer
81 views

How can I map 4GB of RAM memory to 4GB CPU address space [closed]

I'm confused with a situation where there is 4GB of CPU address space and I have 4GB of RAM memory. Now is it possible to map this whole 4GB of RAM memory to CPU address space and if so, then where ...
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106 views

What is the relationship between PMU and PEBS for intel CPU?

I know for intel CPU families, there are PMU (Performance Monitoring Unit) and PEBS (Precise Event Based Sampling). What is the relationship between them? Per my understanding, the PMU contains PEBS, ...
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2answers
68 views

How to find out computer architecture WITHOUT access to Control Panel

NOTE: I do have access in File Explorer to browse the entire filesystem. Extra details: I am at a library in my school running Windows 7 Enterprise. I am bored, so I am trying to figure out ways to ...
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1answer
106 views

Computer Architecture : DDR3 Memory Technology - Slot Capacity Scaling

Speaking in terms of Computer Architecture, what are the characteristics embedded in a DDR3 memory module or the host slot, such that a user cannot put a larger RAM than the per-slot specification of ...
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1answer
758 views

What are functional unit and control logic of a cpu?

From the book Modern Operating systems; The abundance of transistors on a single chip is leading to a problem: what to do with all of them? We saw one approach above: superscalar ...
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1answer
96 views

What does “book” mean in the output of 'lscpu -p'?

On Linux, the lscpu -p command outputs lots of information about the CPU architecture. One of the columns is the "book number". What does "book" mean in this context? EDIT: the documentation of lscpu ...
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34 views

Why is cache leakage power consumption higher than other hardware units?

Is it correct that caches (SRAM cells) have higher leakage power compared to other hardware units with the same area such as ALU? And if so, why is the case?
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2answers
497 views

Would Like to Upgrade CPU of hp pavilion touchsmart 11z-e000 Notebook

I recently bought a HP TouchSmart 11Z-e000 Laptop but I am not happy with performae. It is using AMD A4 CPU with 4 GB RAM. I think the RAM is enough. Culprit here is CPU for the slow performance. I ...
5
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2answers
386 views

32-bit to 64-bit skipping 48-bit?

Computer architecture upgraded from 16-bit to 32-bit to 64-bit. What was the logic for skipping 48-bit? What reasoning was used to upgrade to 64-bit and not some other exponent? The following tables ...
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13answers
15k views

Why doesn't “add more cores” face the same physical limitations as “make the CPU faster”?

In 2014, I hear a lot of programming languages touted for their concurrency features. Concurrency is said to be crucial for performance gains. In making this statement, many people point back to a ...
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2answers
428 views

Defining 32-bit or 64-bit processor requirements [duplicate]

My knowledge of computer hardware is fairly extensive, however it is apparent that this is not the case when considering types of operating systems. I've gone by the rule of thumb for years that if a ...
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2answers
392 views

What is the on-chip network topology of an Intel Core i7 (or i3 or i5) processor?

What is the topology of the interconnection network within an Intel core i7 ,i3 or i5 processor? Is it using a: Crossbar Ring Hypercube Mesh Butterfly or what ?
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33 views

How are graphics produced on the screen?

I have been trying to get a complete answer to this for a long time and I know it is complex. For example lets say we wanted to produce the character 'H' on the screen. H is 72 in ascii or 48 in Hex ...
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0answers
945 views

How to determine control/data/address bus width

I am hoping you guys can help. I need to know how to calculate the control bus, address bus, and data bus width of a hypothetical CPU. A computer is word addressable with a 64 bit word size and ...
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2answers
87 views

How does an instruction in a CPU report that is has finished?

When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly ...
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2answers
541 views

Are 64-bit processors “faster” than 32-bit ones, simply because they are 64-bits? [duplicate]

I have pondered that some say "32-bit is old news" because you are limited in RAM without cutting around, such as with PAE. Assuming first that the following factors weigh in on the processor's speed ...
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1answer
210 views

Confusing info from /proc/cpuinfo: CPU Frequency:

I ran a 'cat /proc/cpuinfo' on a node I'm using and obtained the following: processor : 13 vendor_id : GenuineIntel cpu family : 6 model : 62 model ...
7
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1answer
110 views

How do general binaries take advantage from new instructionsets on new CPUs

With every release of a new processor, there are changes to the instructionset the processor supports. For example, Haswell has Advanced Vector Extensions. However, when I run a program on a PC with a ...