CPU Architecture refers to a collection of parameters about the design of CPU realized by its manufacturer, such as: its bit-ness or data bus width (16, 32, 64 bits) , Instruction Set (RISC, CISC,...), Memory Management, Threading, Virtualization support, etc

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Instruction assignment with multiple CPUs

Maybe this is a stupid question but I am trying to gain a better understanding of hardware inner workings... If a machine has two or more CPUs, which hardware component is actually responsible for ...
5
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1answer
481 views

Does a CPU clock frequency vary on-demand?

On my machine (not a personal computer), I have 24 cores (2.4GHz) and I currently don't have any important process running. Right now, are all of my 24 cores running/vibrating at 2.4GHz or are some of ...
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0answers
30 views

Is there a pentium equivalent of any i-series processor?

I have a confusion with speed of processors and I want to know what makes say, i3 faster than pentium processor which pentium doesn't have? If we add more GHz to pentium will it be same as i3 in some ...
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What's the difference between a hardware register and a memory-mapped register?

This has been puzzling, so I'll lay it all out here. Apparently, through MMIO, you can access external devices using a certain memory-mapped address, which would then be re-routed to that device ...
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1answer
387 views

What are functional unit and control logic of a cpu?

From the book Modern Operating systems; The abundance of transistors on a single chip is leading to a problem: what to do with all of them? We saw one approach above: superscalar ...
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2answers
40 views

RAM Limitation on 64 bit arch

I see that there are a lot of places mentioning 16 EB RAM limitation... However, isn't a modern register 64 bit? and if so, 2^64 should point to the number of registers possible and since they are ...
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1answer
114 views

Windows 10 upgrade 32bit to x64

I have a windows 8.1 32bit installation with 4GB of RAM and a x64 capable CPU. I've upgraded the RAM to 8GB and want to do the Windows 10 upgrade... as far as I'm aware the upgrade will do a like for ...
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3answers
1k views

Why are newer generations of processors faster at the same clock speed?

Why, for example, would a 2.66 GHz dual-core Core i5 be faster than a 2.66 GHz Core 2 Duo, which is also dual-core? Is this because of newer instructions that can process information in fewer clock ...
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2answers
36 views

Difference between a read and load

What is the major difference between and read and load and a write and store? I know it is a very basic question, but somehow not able to get it.
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26 views

My Single-Threaded CPU-Overloading apps use a percent of a thread, graphs shows different results

I made very simple C++ app that contains an empty while(true); loop, I tried with both optimized (-O2) and without optimization, both gave the same result in Task Manager, I even tried same Java and ...
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3answers
273 views

Hardware. What is the difference between a port and a bank?

Especially, these days, the distinction between them is very confusing.. For example, NVidia's shared memory is 32-banked, so what they say is in one cycle, 32 data can come out at the same time... ...
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952 views

Direct Memory Access(DMA) controllers for intel

Does intel in it's current generation of processors provide any Direct Memory Access(DMA) controllers? If yes is it built into the chip? http://en.wikipedia.org/wiki/Direct_memory_access
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3answers
99 views

CISC and VLIW, and instruction and opcode

From http://en.wikipedia.org/wiki/Instruction_set CISC processors include "complex" instructions in their instruction set. A single "complex" instruction does something that may take many ...
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2answers
70 views

Why is it said that 'The longer the pipeline, higher the processor clock rate' [duplicate]

I have been recently going through the hyper threading technology of Pentium 4. The number of pipeline stages is high in P4 and is said that it will increase the speed of clock rate. How is that ...
2
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1answer
5k views

How many registers does Intel® Core™ i7-3770T Processor have?

I've been looking at this website: http://ark.intel.com/products/65525/Intel-Core-i7-3770T-Processor-8M-Cache-up-to-3_70-GHz But I can't figure out the number of registers.
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195 views

How many bits are in the address field for a directly mapped cache?

Here is the problem I am working on: The Problem: " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 ...
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2answers
124 views

What does “address resolution at the byte level” mean?

Here is the problem I am working on The Problem :A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address ...
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1answer
71 views

How many words can be in the address space?

Here is the problem I am working on The Problem: A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. How many words can in be in the address ...
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1answer
318 views

Is the amount of NUMA nodes always equal to sockets?

I have used lscpu to check two servers configuration: [root@localhost ~]# lscpu Architecture: x86_64 ...... Core(s) per socket: 1 Socket(s): 1 NUMA node(s): 1 ...
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1answer
11k views

Why is SRAM faster than DRAM?

In modern multi-core processors, the processor caches (L1,L2 and L3) are made up of SRAM with decreasing speeds(L2 caches are higher speed SRAM than L3 caches which is a cost trade-off). The main ...
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2answers
118 views

If a 32 bit CPU has a 64bit bus system, is it 64 bit or 32 bit?

Let's say the internal registers of a CPU are 32 bits wide. But the CPU has a 64 bit system bus and the two separate pipelines are receiving information simultaneously, is it considered a 32bit ...
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36 views

Why is Pentium 4 Prescott slow compared to Pentium M? [duplicate]

I was benchmarking if it is worth to put loop inside a callback function so I tested fourth order Runge-Kutta of on y'=y in C++, all with gcc 5.1 on Ubuntu with compilation command g++ -std=c++11 -O3 ...
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47 views

Do virtual machines not allow all host CPU extensions?

For convenience's sake I'm trying to run an otherwise "regular" installation of Gentoo Linux as a guest inside VirtualBox on a Windows 7 host. I bootstrapped the installation by using VirtualBox, ...
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2answers
52 views

How does a CPU decide which transistors to use? [closed]

Perhaps I'm not thinking about this correctly, but when you give the CPU a command such as Multiply Registers (MR) R2,R4 how does it decide which logic gates it will use, is it just the first gates ...
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1answer
46 views

Where is the CPUID string located in the CPU?

I'm a newbie to CPU architectures and design, I came up with the following question: Where is the CPUID string (like "GenuineIntel") stored? Is it hard-coded in the microcode ROM? Or is CPUID a ...
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1answer
56 views

How can I map 4GB of RAM memory to 4GB CPU address space [closed]

I'm confused with a situation where there is 4GB of CPU address space and I have 4GB of RAM memory. Now is it possible to map this whole 4GB of RAM memory to CPU address space and if so, then where ...
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2answers
63 views

How does an instruction in a CPU report that is has finished?

When an instruction is sent to a CPU, that may take multiple clock cycles to complete, when does the CPU know that the instruction has finished and can start processing the next one? I'm mostly ...
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0answers
62 views

What is the relationship between PMU and PEBS for intel CPU?

I know for intel CPU families, there are PMU (Performance Monitoring Unit) and PEBS (Precise Event Based Sampling). What is the relationship between them? Per my understanding, the PMU contains PEBS, ...
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2answers
38 views

How to find out computer architecture WITHOUT access to Control Panel

NOTE: I do have access in File Explorer to browse the entire filesystem. Extra details: I am at a library in my school running Windows 7 Enterprise. I am bored, so I am trying to figure out ways to ...
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1answer
84 views

Computer Architecture : DDR3 Memory Technology - Slot Capacity Scaling

Speaking in terms of Computer Architecture, what are the characteristics embedded in a DDR3 memory module or the host slot, such that a user cannot put a larger RAM than the per-slot specification of ...
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2answers
282 views

Would Like to Upgrade CPU of hp pavilion touchsmart 11z-e000 Notebook

I recently bought a HP TouchSmart 11Z-e000 Laptop but I am not happy with performae. It is using AMD A4 CPU with 4 GB RAM. I think the RAM is enough. Culprit here is CPU for the slow performance. I ...
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689 views

How to determine control/data/address bus width

I am hoping you guys can help. I need to know how to calculate the control bus, address bus, and data bus width of a hypothetical CPU. A computer is word addressable with a 64 bit word size and ...
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1answer
71 views

What does “book” mean in the output of 'lscpu -p'?

On Linux, the lscpu -p command outputs lots of information about the CPU architecture. One of the columns is the "book number". What does "book" mean in this context? EDIT: the documentation of lscpu ...
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32 views

Why is cache leakage power consumption higher than other hardware units?

Is it correct that caches (SRAM cells) have higher leakage power compared to other hardware units with the same area such as ALU? And if so, why is the case?
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13answers
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Why doesn't “add more cores” face the same physical limitations as “make the CPU faster”?

In 2014, I hear a lot of programming languages touted for their concurrency features. Concurrency is said to be crucial for performance gains. In making this statement, many people point back to a ...
5
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2answers
251 views

32-bit to 64-bit skipping 48-bit?

Computer architecture upgraded from 16-bit to 32-bit to 64-bit. What was the logic for skipping 48-bit? What reasoning was used to upgrade to 64-bit and not some other exponent? The following tables ...
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7answers
1k views

Why does the heat production increase as the clockrate of a CPU increases?

The whole multi-core debate got me thinking. It's much easier to produce two cores (in one package) then speeding up one core by a factor of two. Why exactly is this? I googled a bit, but found ...
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4answers
1k views

Does the 6502 put FF in the stack pointer register as soon as it gets power for the first time?

I'm reading about the 6502 processor's instruction set from the many links at 6502.org, and one tutorial states: The stack pointer (S) points to a byte on Page 1, that is, to a byte whose address ...
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2answers
373 views

Defining 32-bit or 64-bit processor requirements [duplicate]

My knowledge of computer hardware is fairly extensive, however it is apparent that this is not the case when considering types of operating systems. I've gone by the rule of thumb for years that if a ...
2
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3answers
10k views

Which Windows 7 Version (32 bit or 64 bit) should I install on a new MacBook Pro with 4 GB of RAM?

I have just bought a brand new MacBook Pro with 4 GB RAM, and was wondering which Windows 7 version 32 bit or 64 bit I should install with BootCamp, in order to do Visual Studio development? Is ...
9
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4answers
13k views
5
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3answers
6k views

What do the terms “asynchronous” and “synchronous” mean, with respect to the definition of an interrupt?

Quoted from http://en.wikipedia.org/wiki/Interrupt: an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change ...
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2answers
241 views

What is the on-chip network topology of an Intel Core i7 (or i3 or i5) processor?

What is the topology of the interconnection network within an Intel core i7 ,i3 or i5 processor? Is it using a: Crossbar Ring Hypercube Mesh Butterfly or what ?
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0answers
29 views

How are graphics produced on the screen?

I have been trying to get a complete answer to this for a long time and I know it is complex. For example lets say we wanted to produce the character 'H' on the screen. H is 72 in ascii or 48 in Hex ...
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1answer
149 views

Confusing info from /proc/cpuinfo: CPU Frequency:

I ran a 'cat /proc/cpuinfo' on a node I'm using and obtained the following: processor : 13 vendor_id : GenuineIntel cpu family : 6 model : 62 model ...
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3answers
1k views

where does Kernel reside on a multi-core system

Suppose I have a multi-core system, say 4 cores, and in this I pin 3 user process to a 3 CPU's. In such a case, where will the kernel reside? Suppose one of the user process make a system call, or ...
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Are 64-bit processors “faster” than 32-bit ones, simply because they are 64-bits? [duplicate]

I have pondered that some say "32-bit is old news" because you are limited in RAM without cutting around, such as with PAE. Assuming first that the following factors weigh in on the processor's speed ...
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1answer
105 views

How do general binaries take advantage from new instructionsets on new CPUs

With every release of a new processor, there are changes to the instructionset the processor supports. For example, Haswell has Advanced Vector Extensions. However, when I run a program on a PC with a ...
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2answers
149 views

Do emulators parse binary code within files?

I have seen some emulators that claim they execute, and even though they do, their source code shows they don't directly parse every 1 and 0 to determine an instruction. My question is, if the ...
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2answers
322 views

Why CPU emulation is slow [closed]

Different CPU (IA-32, ARM9 etc.) operations should be equivalent in their nature (move, read, write data etc.). It shouldn't be that painful for different CPUs to emulate each other. But seems like ...