CPU Architecture refers to a collection of parameters about the design of CPU realized by its manufacturer, such as: its bit-ness or data bus width (16, 32, 64 bits) , Instruction Set (RISC, CISC,...), Memory Management, Threading, Virtualization support, etc

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Hardware. What is the difference between a port and a bank?

Especially, these days, the distinction between them is very confusing.. For example, NVidia's shared memory is 32-banked, so what they say is in one cycle, 32 data can come out at the same time... ...
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Using 32bit application in 64bit

I am using windows 32 bit VLC media player in 64 bit pc. It is working fine. but my question is that won't it allocate memory according to 32 bit structure? That means though i have 64 bit PC, i ...
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which one of these units is not located in the microprocessor?

I'm doing a test on general computer science and I think the answer sheet is wrong. The question is as follows: which one of these units is not located in the microprocessor? 1) Cache ...
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How to determine control/data/address bus width

I am hoping you guys can help. I need to know how to calculate the control bus, address bus, and data bus width of a hypothetical CPU. A computer is word addressable with a 64 bit word size and ...
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Reading CPU model specific registers on linux

I am running Ubuntu 15.10 but testes it also on Debian. I have Intel i5-5675C processor. I am using msr-tools-1.3 to do it. I am able to read register 0x00001a2 with the following command: rdmsr ...
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What is the relationship between PMU and PEBS for intel CPU?

I know for intel CPU families, there are PMU (Performance Monitoring Unit) and PEBS (Precise Event Based Sampling). What is the relationship between them? Per my understanding, the PMU contains PEBS, ...
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Using UEFI to access CPU features which are locked in BIOS

I have Dell Latitude E6420 with SandyBridge i5-2520M and standard issue Dell BIOS (version A15). In certain situations computer produces annoying high-pitched noise (it is not loud but it is ...
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operations process in a computer

Is it true that all high-level operations in a computer (say, copying, pasting, web surfing, running apps etc) are all finally converted to micro-operations (say, arithmetic, logical and shift) and ...
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Register allocation tables overwrite

Reading about the Xeon processor: the Xeon has two register allocation tables (RATs), each of which handles the mapping of one logical processor's eight architectural integer registers and eight ...
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What debian architecture do I need to download

I'm running a server with a i5 4440 CPU. Now according to the FAQ I thought I need to download the i386 version. Now I searched the internet and found some topics and some friends are telling me I ...
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Why does 'lshw' tell me “32 bits”?

I ran lshw from a LiveUSB, but I'm not entirely clear how to understand one part of the output. In the first part, it says width: 32 bits, but just a few lines down in the CPU details it says width: ...
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Is there a pentium equivalent of any i-series processor?

I have a confusion with speed of processors and I want to know what makes say, i3 faster than pentium processor which pentium doesn't have? If we add more GHz to pentium will it be same as i3 in some ...
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My Single-Threaded CPU-Overloading apps use a percent of a thread, graphs shows different results

I made very simple C++ app that contains an empty while(true); loop, I tried with both optimized (-O2) and without optimization, both gave the same result in Task Manager, I even tried same Java and ...
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How many bits are in the address field for a directly mapped cache?

Here is the problem I am working on: The Problem: " A high speed workstation has 64 bit words and 64 bit addresses with address resolution at the byte level. Assuming a direct mapped cache with 8192 ...
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Do virtual machines not allow all host CPU extensions?

For convenience's sake I'm trying to run an otherwise "regular" installation of Gentoo Linux as a guest inside VirtualBox on a Windows 7 host. I bootstrapped the installation by using VirtualBox, ...
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Why is cache leakage power consumption higher than other hardware units?

Is it correct that caches (SRAM cells) have higher leakage power compared to other hardware units with the same area such as ALU? And if so, why is the case?
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How are graphics produced on the screen?

I have been trying to get a complete answer to this for a long time and I know it is complex. For example lets say we wanted to produce the character 'H' on the screen. H is 72 in ascii or 48 in Hex ...