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bio website sites.google.com/site/…
location Greenbelt, MD, USA
age 48
visits member for 1 year, 7 months
seen 18 hours ago

My utility function appears to be approaching zero.


1d
comment What is the meaning of CPU core?
I am sorry if the above comment was a bit harsh. The original poster was asking a simple question and not looking for a treastise on the tradeoffs in processor design. Your use of "hog wash" triggered a reflex that reacts to the belittling of the complex tradeoffs in processor design. Yes, some marketing has replaced the megahertz myth with the core-count myth, but both are at best coarse measures of performance which as you noted "all depends" (workload, non-core CPU and non-CPU system components).
1d
comment What is the meaning of CPU core?
Real world performance is much more complex than clock frequency. A higher performance single-threaded core can be limited by memory latency (ignoring diminishing performance returns for power and chip area budgets). Hardware multithreading increases the amount of memory-level parallelism, allowing more memory latency to be hidden (it also helps with branch resolution and execution latency). Multicore provides similar memory latency hiding benefits without the L1 cache contention. These techniques can turn a memory latency bottleneck into a memory bandwidth bottleneck.
Jul
11
comment Where exactly L1, L2 and L3 Caches located in computer?
If by chip you mean silicon die, then the last level of cache can be off chip. E.g., IBM's zEC12 (en.wikipedia.org/wiki/IBM_zEC12_(microprocessor)) uses a multichip module with six processor chips and two shared cache chips with L4 cache. Intel's Crystal Well also provides an L4 off-chip cache (also using eDRAM).
Jul
4
answered Difference between “network RAM” and “distributed shared memory” (DSM)
Jun
29
comment Are there two seperated schedulers in major operating systems, one for processes and one for their threads?
This is somewhat OS-dependent. The currently preferred mechanism is 1:1 thread scheduling where the OS scheduling unit maps to a single thread. The M:N hybrid model has been used in the past where application layer scheduling was applied on top of OS scheduling. (See Wikipedia's Thread Models article section)
Jun
20
comment Meaning of computer architecture
Computer architecture vs. organization: organization is more commonly (in more recent times) called microarchitecture, the implementation details above transistor-level; c.a. can refer to the software interface ("the structure of a computer that a machine language programmer must understand to write a correct (timing independent) program for that machine" from "Architecture of the IBM System/360") or to the field of study which includes both architecture and microarchitecture.
Jun
20
comment What architecture to choose with 2 GB of RAM in the computer
What are the security improvements? No-eXecute is supported in 32-bit by using PAE.
Jun
19
comment Science computation approach & errors
"small changes in input parameters should produce correspondingly small changes in the output"—except for chaotic systems. ☺
Jun
15
comment Difference between “network RAM” and “distributed shared memory” (DSM)
This page defines network RAM as remote DRAM swap space. I.e., if one node is underutilizing memory capacity, using it's DRAM as swap space for a node overutilizing its memory capacity can provide lower latency. (Semi-)local flash would have a different set of tradeoffs. As swap space network RAM is not directly addressable and page-sized blocks might be friendlier to non-RDMA-capable Ethernet. (I might come back and expand this into an answer but don't count on it.)
May
31
comment Are lower TDP CPUs slower?
It might be worth noting that lower TDP bins are typically more expensive (why give away something valuable to some users—lower energy use—for free?). Like speed binning, TDP binning is largely a result of manufacturing variation. Also, I think that if a thermal solution designed for a higher TDP is used, there might be greater opportunity for using higher turbo frequencies.
May
9
comment Why does the same RAM chip benchmark 2x faster on Intel CPUs?
Without information about the benchmark (other than "uncached reads") or the systems tested (other than processor vendor and memory module), how can one draw any conclusions? The explanation could be as simple as the Intel systems having four memory channels and the AMD systems having two. Perhaps the AMD system is using an in-CPU GPU with the GPU taking some of the memory bandwidth? Without details one can only guess.
May
8
comment CPU die sizes and manufacturing process
There are also transistors that do not scale such as those driving I/O pins (probably not significant). There are also areas of a chip whose size is wire limited; wire width has not shrunk as fast. Complicating such an evaluation, the 32nm to 22nm change also had a transition to FinFET. The Electrical Engineering SE could probably provide a more detailed answer. (I am not an EE, have not played one on television and did not stay at a Holiday Inn Express last night.☺)
May
3
answered Intel Processor Family
Apr
28
comment How do modern smartphones compare to Apollo mission computers?
You should probably include a [sic] in the quote after "in Hz" since clearly "in kHz" was meant, perhaps with a parenthetical note to clarify.
Apr
28
comment How do modern smartphones compare to Apollo mission computers?
You should make a distinction between the Apollo Guidance Computer and the computers used on the ground (presumably excluding any used for design or manufacture and perhaps also any used for training simulation), which could also be considered part of the mission. Also Moore's Law concerned transistors per chip not performance.
Apr
23
answered Whats the difference between physical and virtual cache?
Apr
23
comment Whats the difference between physical and virtual cache?
Do you mean a virtually addressed (virtually indexed/virtually tagged) cache?
Apr
22
comment In what operations do processors internally use bitwise computations?
Don't forget modulo (%) a power of two, which can use and.
Apr
15
answered Couldn't find the specific details for a IBM x3850 server
Apr
14
comment What is the difference between multithreading and hyperthreading?
Suggested edits that change the content (i.e., not just grammar/typo corrections or rephrasing for clarity) are likely to be rejected.