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Apr
15
comment Are cores in a CPU package always identical?
Note: the question is tagged Intel, so I am assuming the OP is concerned with Intel x86. So far Intel has not adopted heterogeneous multicore (though due to process variation it might be possible to use turboboost more often on one core than another; the same would apply to user overclocking).
Mar
30
comment Can a CPU cache similar calculations?
Another vaguely related optimization that has been proposed academically involves trace caches (though a predecoded instruction cache could accomplish some of the proposed optimizations). These do not cache the results of computations but analyze the code stream and cache transformations of the code (sometimes depending on control flow, which might make them count as operand-based caching of "computation").
Mar
30
comment Can a CPU cache similar calculations?
Hardware memoization has been proposed academically, but I am not aware of any implementation. Newton-Raphson division is one attractive target for memoization since division is expensive and NR already involves a table look-up for an approximate inverse and the tag would only need to be for one value. (Value prediction is a similar concept, but value prediction is speculative, checking the prediction with an actual result rather than determining a valid value by a tag comparison.)
Mar
26
comment How to find out if a CPU has an MMU
A memory protection unit can provide isolation (it differs from a TLB/MMU in not supporting translation, so paging is not supported). Microkernel OSes often have an emphasis on least privilege which provides greater isolation, typically at the cost of performance. Hardware support for single address space OSes (e.g., permission tables and permission lookaside buffers or page groups [e.g., provided by Itanium]) may reduce the cost of finer-grained permissions in privileged software.
Feb
23
comment Multitasking illusion on a single threaded processor?
A GUI could remain responsive because user input generates an interrupt from which the OS could then call a specific handler in the application to perform the GUI work and that handler could return to the background task. Similarly, asynchronous I/O allows (e.g.) disk access without stalling. In addition to timer and I/O interrupts, system calls also provide an opportunity for the OS to perform scheduling.
Feb
9
comment what are advantages of northbridge chipset
Athlon64 was first only in the mainstream x86 market (Wikipedia mentions DEC Alpha 21066 and HP PA-7300LC). Integration can also reduce system cost but constrains system diversity by tying more aspects to the chip vendor (system vendors using merchant CPUs have less opportunity to differentiate their products). A distinct memory controller can also be connected to two processor sockets, providing small-scale UMA. A shared I/O and memory interface includes the usual shared vs. partitioned tradeoffs.
Feb
4
comment Does DDR RAM also have a minimum bandwidth?
"Under load" means making accesses (i.e., an arbitrarily long queue of ordered accesses is available). Under a particularly perverse access pattern (e.g., involving same bank different row accesses) the achieved bandwidth is much lower than the best case where the same row is accessed multiple times and different banks are accessed (which can even allow refreshing to be done in parallel). Max bandwidth assumes best case access pattern, min bandwidth assumes worst case access pattern.
Feb
4
comment Does DDR RAM also have a minimum bandwidth?
I think the question is assuming "under load".
Feb
4
comment Does DDR RAM also have a minimum bandwidth?
My guess would be that the worst "reasonable" case with a single rank would be a sequence of single reads to different rows within a single DRAM bank (a sequence of ACTIVATE, READ, PRECHARGE commands to the same bank) with the added overhead of occasional REFRESH commands (some of which are to other banks, allowing some parallel operation). If burst chop is used (which is pushing reasonableness), the bandwidth would be halved.
Jan
27
comment How many registers does Intel® Core™ i7-3770T Processor have?
@einpoklum With the recent addition of gather (and scatter in Xeon Phi, if I remember correctly), SIMD registers can be used for addressing memory directly and it might be less impractical to treat SIMD registers as GPRs, though such would still be very inefficient.
Jan
27
comment How many registers does Intel® Core™ i7-3770T Processor have?
@einpoklum General purpose register is a bit of a misnomer in that most ISAs (m88k being an exception) do not support FP operations in GPRs, but x87 (from what I recall) do not support memory addressing (I do not know how general the integer support was for x87 registers when used as MMX registers). (With respect to SIMD registers, the question asked about registers [I suppose one could also include various others like segment registers and flags and even MSRs.]. SSE/AVX registers support scalar FP operations (I don't know if scalar integer operations are supported.).)
Jan
5
answered How does physical distance between processor and memory/cache affect data transfer speeds
Dec
17
awarded  Yearling
Nov
29
comment Whats the difference between physical and virtual cache?
@PeterCordes I was calling the offset within a page part of the physical address (for those bits virtual === physical). If one is emphasizing latency, one might tend to call such virtually indexed; if one is emphasizing the lack of aliasing problems, one might tend to call such physically indexed.
Nov
4
comment Why is the 5960x Haswell and not Broadwell?
The 5960x that the original poster specifically mentioned is a 22nm (Haswell, 4th Gen.) part (see Intel ARK) when the 5* series should be 5th Gen.
Nov
3
comment Intelligent Memory(IM) vs Processing In Memory(PIM)
The University of California Berkeley IRAM page might be a good source of information.
Nov
3
comment Intelligent Memory(IM) vs Processing In Memory(PIM)
@FrankThomas Intelligent RAM was proposed by David Patterson et al. ("A case for intelligent RAM: IRAM" (PDF), 1997) and uses a full-featured, SIMD-supporting processor. As I understand it, IRAM is a particular kind of PIM. Some PIM ideas focus on specific operations; I would include 3DRAM — a graphics RAM that supported simple ALU ops with memory writes — as a limited form of PIM. With recent stacked DRAM such as Hybrid Memory Cube, Processor Near Memory may be an interesting alternative (avoid logic vs. DRAM process issues).
Jul
15
comment How can a processor execute more IPS than its frequency?
@PeterCordes There are different voting philosophies. Some claim "useful" is the only criterion, others consider relative merit (for answers). I tend to consider absolute vote count ("nice", "good", "great" post badges imply such should be considered) as well as relative vote count (which helps answer ranking). Surprisingly Meta.SE does not seem to have much on this topic and "How should I vote?" doesn't even have an answer!
Jul
15
comment How can a processor execute more IPS than its frequency?
Self-promotion: How can a CPU deliver more than one instruction per cycle? was asked on the Electrical Engineering Stack Exchange (my answer was accepted and perhaps too highly upvoted).
Jul
6
comment Why aren't there PCIe RAM expansions?
Probably another factor deprecating RAM cards was the move from 32-bit processors to 64-bit processors. More recently, PCIe flash (usually with a DRAM cache) has taken a similar role.