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comment what are advantages of northbridge chipset
Athlon64 was first only in the mainstream x86 market (Wikipedia mentions DEC Alpha 21066 and HP PA-7300LC). Integration can also reduce system cost but constrains system diversity by tying more aspects to the chip vendor (system vendors using merchant CPUs have less opportunity to differentiate their products). A distinct memory controller can also be connected to two processor sockets, providing small-scale UMA. A shared I/O and memory interface includes the usual shared vs. partitioned tradeoffs.
Feb
4
comment Does DDR RAM also have a minimum bandwidth?
"Under load" means making accesses (i.e., an arbitrarily long queue of ordered accesses is available). Under a particularly perverse access pattern (e.g., involving same bank different row accesses) the achieved bandwidth is much lower than the best case where the same row is accessed multiple times and different banks are accessed (which can even allow refreshing to be done in parallel). Max bandwidth assumes best case access pattern, min bandwidth assumes worst case access pattern.
Feb
4
comment Does DDR RAM also have a minimum bandwidth?
I think the question is assuming "under load".
Feb
4
comment Does DDR RAM also have a minimum bandwidth?
My guess would be that the worst "reasonable" case with a single rank would be a sequence of single reads to different rows within a single DRAM bank (a sequence of ACTIVATE, READ, PRECHARGE commands to the same bank) with the added overhead of occasional REFRESH commands (some of which are to other banks, allowing some parallel operation). If burst chop is used (which is pushing reasonableness), the bandwidth would be halved.
Jan
27
comment How many registers does Intel® Core™ i7-3770T Processor have?
@einpoklum With the recent addition of gather (and scatter in Xeon Phi, if I remember correctly), SIMD registers can be used for addressing memory directly and it might be less impractical to treat SIMD registers as GPRs, though such would still be very inefficient.
Jan
27
comment How many registers does Intel® Core™ i7-3770T Processor have?
@einpoklum General purpose register is a bit of a misnomer in that most ISAs (m88k being an exception) do not support FP operations in GPRs, but x87 (from what I recall) do not support memory addressing (I do not know how general the integer support was for x87 registers when used as MMX registers). (With respect to SIMD registers, the question asked about registers [I suppose one could also include various others like segment registers and flags and even MSRs.]. SSE/AVX registers support scalar FP operations (I don't know if scalar integer operations are supported.).)
Jan
5
answered How does physical distance between processor and memory/cache affect data transfer speeds
Dec
17
awarded  Yearling
Nov
29
comment Whats the difference between physical and virtual cache?
@PeterCordes I was calling the offset within a page part of the physical address (for those bits virtual === physical). If one is emphasizing latency, one might tend to call such virtually indexed; if one is emphasizing the lack of aliasing problems, one might tend to call such physically indexed.
Nov
4
comment Why is the 5960x Haswell and not Broadwell?
The 5960x that the original poster specifically mentioned is a 22nm (Haswell, 4th Gen.) part (see Intel ARK) when the 5* series should be 5th Gen.
Nov
3
comment Intelligent Memory(IM) vs Processing In Memory(PIM)
The University of California Berkeley IRAM page might be a good source of information.
Nov
3
comment Intelligent Memory(IM) vs Processing In Memory(PIM)
@FrankThomas Intelligent RAM was proposed by David Patterson et al. ("A case for intelligent RAM: IRAM" (PDF), 1997) and uses a full-featured, SIMD-supporting processor. As I understand it, IRAM is a particular kind of PIM. Some PIM ideas focus on specific operations; I would include 3DRAM — a graphics RAM that supported simple ALU ops with memory writes — as a limited form of PIM. With recent stacked DRAM such as Hybrid Memory Cube, Processor Near Memory may be an interesting alternative (avoid logic vs. DRAM process issues).
Jul
15
comment How can a processor execute more IPS than its frequency?
@PeterCordes There are different voting philosophies. Some claim "useful" is the only criterion, others consider relative merit (for answers). I tend to consider absolute vote count ("nice", "good", "great" post badges imply such should be considered) as well as relative vote count (which helps answer ranking). Surprisingly Meta.SE does not seem to have much on this topic and "How should I vote?" doesn't even have an answer!
Jul
15
comment How can a processor execute more IPS than its frequency?
Self-promotion: How can a CPU deliver more than one instruction per cycle? was asked on the Electrical Engineering Stack Exchange (my answer was accepted and perhaps too highly upvoted).
Jul
6
comment Why aren't there PCIe RAM expansions?
Probably another factor deprecating RAM cards was the move from 32-bit processors to 64-bit processors. More recently, PCIe flash (usually with a DRAM cache) has taken a similar role.
May
22
comment Sharing hardware resources through network: specifically RAM
Note that for some workloads, random access latency is more important than bandwidth (and I suspect your disk bandwidth figure was for large accesses not random 4KiB chunks). Even with networking overheads, transferring 4KiB directly from one system to another would probably be faster than average disk access (with seek, settle, and rotational delays). Before SSDs became popular, there was research on using other systems' RAM for swap space. FuaZe's answer of moving work to the larger system seems more practical.
May
10
comment Content of volatile memory after power loss
It might be worth noting that the interpretation of low charge in the DRAM cell (capacitor) is arbitrary (i.e., low charge could be interpreted as a binary 1). It is not even necessary for every bit cell to be interpreted in the same manner (the memory controller could interpret 32 uncharged bit cells as 0xDEADBEEF). (For Flash one could even argue that the convention of interpreting a freshly erased block as all 1s is less desirable as zero initialization is more common, but I doubt such is a significant consideration.)
Apr
26
comment Why are newer generations of processors faster at the same clock speed?
Improvements in energy efficiency are also a factor given the power wall.
Mar
9
comment How can Windows dump the complete RAM in the hibernation file so fast?
Pages that are not dirty is a more general statement of "paged out to the swap file", this would include executables. (Since executables are somewhat fragmented on disk, this could slow wake-up.) In addition, clean file buffers can presumably just be dropped even if they are not part of a memory mapped file.
Feb
25
comment What are NAF, NAES on RAM?
Since there are parts with NBF, the second letter likely identifies some sequence where less than 26 values are expected to exist. A quick Googling did not find any Kingmax DIMM datasheets (datasheets often provide information on how part numbers are generated), so such information might not be readily available. If you are especially curious, you could contact Kingmax's sales (their contact page gives email addresses).