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bio website sites.google.com/site/…
location Silver Spring, Maryland
age 49
visits member for 1 year, 11 months
seen 8 hours ago

Move along. Nothing (much) to see.


Nov
16
comment In L1, L2 cache and DRAM, is sequential access faster than random access?
DRAM is not perfectly random access, a read from an open DRAM page/row will be faster than when the bank has no page/row open (since a row ACTIVATE command must be processed by the bank) much less when another page/row is open in the same bank of the DRAM (since that bank needs to process a PRECHARGE command before the row ACTIVATE command can open a new page).
Nov
16
comment Why is loading chunks of data into the cpu cache an efficient way of processing?
My answer to "Why would computers transfer data and instructions from main memory to cache in blocks when this means a single cache miss may overwrite a lot" (a closed question) may sufficiently answer your question.
Nov
16
comment Virtually Indexed Physically Tagged Cache
Since the index bits are taken from the virtual address and must match the physical address (assuming reprobing is not done on a cache miss to detect aliases or page coloring used to avoid them) and the page size is 1 KiB, there will be 10 bits of virtual address that are also physical and 3 of those bits are used for the offset into the 8-byte cache line, so 7 bits can be used to index the cache (so 128 lines with a direct-mapped cache).
Nov
14
comment Byte addressable memory and ISA
Quick pseudo-answer: instruction size is independent of data register size; data buses to main memory are often wider and typically used to fill a cache block at a time (over multiple "beats" [twice bus cycle for DDR]), the connection between L1 cache and the core may be wider than the core's general purpose registers to support load pair/multiple operations or single access FP/SIMD register load/store (when such are larger than the GPRs) and two banks may be accessed simultaneously to support unaligned accesses. (Icache may also provide more than 1 instruction per cycle.)
Nov
12
answered What does the BASE clock speed of an Intel CPU really signify, now that we have Turbo Boost and SpeedStep
Nov
7
comment Why a disk drive could not be connected (physically) to 2+ computers?
+! Linking to Wikipedia's list of shared-disk file systems might be worthwhile.
Nov
1
comment Why does a CPU with lower frequency score better than one with more?
@LưuVĩnhPhúc Again, I agree (I can't say I really like the chosen benchmark, especially with the lack of sub-test results). Single figure of merit is not especially useful (unless the benchmark happens to match the user's targeted workload or at least allow easy fudge factoring based on known traits like mem. bw, LLC size, etc.). However, the OP was asking about results from the specific benchmark. If I wasn't lazy, I would check the SPEC CPU database for results from similar processors. (Sadly, SPEC allows autopar results in base, which makes single-thread results less available.)
Nov
1
comment Why does a CPU with lower frequency score better than one with more?
@LưuVĩnhPhúc I agree. Yet I get the impression that the multithreaded benchmark is more like SPEC Int Rate (each thread runs the same program) which scales relatively well, though the Physics and String Sorting tests (working set 30 MiB and 25 MiB, respectively) might place a higher burden on the memory system. No sub-test values are given, so reasoning about results is difficult. (BTW, in this case 2x cores/threads → 2.07x performance [without turboboost increasing frequency by 40%!}, so obviously there are other factors [cf. 17% faster in single thread].)
Oct
31
comment what does 2 core 4 threads mean in cpu?
@Ramhound You presumably meant 4 instruction streams. Since the i5 is superscalar it can execute multiple instructions in parallel even from a single instruction stream. Simultaneous multithreading allows thread-level parallelism to be converted into instruction-level parallelism, increasing utilization of execution resources.
Oct
31
comment Why does a CPU with lower frequency score better than one with more?
In single-thread operation the E3 is likely to Turboboost to 3.5 GHz, removing a large portion of the frequency difference. (Without more details about the sub-benchmarks, one could only speculate about why the more recent design at lower frequency performs better.)
Oct
31
comment Why does a CPU with lower frequency score better than one with more?
From the PassMark site: "To ensure that the full CPU power of a PC system is realized, PerformanceTest runs each CPU test on all available CPUs. Specifically, PerformanceTest runs one simultaneous CPU test for every logical CPU (Hyper-threaded); physical CPU core (dual core) or physical CPU package (multiple CPU chips). So hypothetically if you have a PC that has two CPUs, each with dual cores that use hyper-threading then PerformanceTest will run eight simultaneous tests." So core count matters.
Oct
20
comment How to find out if a CPU has an MMU
uCLinux and FreeRTOS (and presumably at least some commercial RTOSes) support MPUs (I don't know if these would count as "common"; the really tiny systems probably avoid MPUs and the moderately large systems may use full MMUs [an MPU may also be used only to protect privileged from unprivileged code]). (The main distinction between an MPU and an MMU is that an MMU includes support for address translation, though sometimes "MMU" is used to include MPUs.) The edit is decent (I already upvoted, and i don't appreciate this enough for a bounty).
Oct
20
comment How to find out if a CPU has an MMU
An MMU is not required for memory protection (a memory protection unit would suffice) and many Real Time OSes do not use virtual memory.
Oct
20
comment How to find out if a CPU has an MMU
ARM M profile and R profile processors do not support MMUs (they do allow, but not require, a memory protection unit to be implemented); these certainly include some "modern processors". UCLinux is a "modern operating system" that does not require an MMU and Real Time OSes generally do not require MMUs.
Oct
10
comment What does “book” mean in the output of 'lscpu -p'?
Books are also used in some POWER systems, e.g., the IBM Power 795 server can have (from table) "Processor books Up to eight" and up to 32 sockets.
Oct
6
comment TLB access in SMT processors
@aminfar Threads within a process (in the usual way that threads are handled) do not have different page access permissions or other metadata and so do not need any distinction in the TLB.
Oct
5
comment TLB access in SMT processors
@aminfar The section you cite mentions Address Space Numbers (the same thing as ASIDs, sometimes called Process IDs), which are defined for the Alpha ISA. (Number is probably a more correct but less common name since numbers may be reused [with appropriate TLB invalidations] so they are not unique identifiers which is somewhat implied by ID.) These are the "extra bits" that distinguish the pages from different processes (address spaces).
Oct
5
comment Is Modern Computers based on Von Neumann Model?
@aminfar Yes, they are executed out-of-order (and sometime in parallel) internally but still abide by the serial execution model of the architecture (i.e., commit in order).
Oct
4
comment TLB access in SMT processors
Many ISAs support Address Space IDs, which allow a single TLB to be shared by multiple processes/address spaces. (I think x86 somewhat recently added this feature; I know it has such for virtual machines, initially only 1 bit, but latter extended, if I recall correctly.) Without such "tag extensions", the TLB would typically be partitioned (much like the return address predictor and some other structures).
Sep
25
answered Is Modern Computers based on Von Neumann Model?