645 reputation
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bio website sites.google.com/site/…
location Silver Spring, Maryland
age 49
visits member for 2 years, 3 months
seen yesterday

Move along. Nothing (much) to see.


Mar
9
comment How can Windows dump the complete RAM in the hibernation file so fast?
Pages that are not dirty is a more general statement of "paged out to the swap file", this would include executables. (Since executables are somewhat fragmented on disk, this could slow wake-up.) In addition, clean file buffers can presumably just be dropped even if they are not part of a memory mapped file.
Feb
25
comment What are NAF, NAES on RAM?
Since there are parts with NBF, the second letter likely identifies some sequence where less than 26 values are expected to exist. A quick Googling did not find any Kingmax DIMM datasheets (datasheets often provide information on how part numbers are generated), so such information might not be readily available. If you are especially curious, you could contact Kingmax's sales (their contact page gives email addresses).
Feb
17
awarded  Excavator
Feb
17
revised Can a single-threaded program be made to use multiple cores?
capitalized CPU, modest rephrasing
Feb
17
answered Can a single-threaded program be made to use multiple cores?
Feb
17
suggested approved edit on Can a single-threaded program be made to use multiple cores?
Jan
29
awarded  Citizen Patrol
Jan
28
comment Can SMT give worse performance than normal CPU?
Conflict misses are also a problem. DRAM accesses can also have a conflict effect increasing the amount of PRECHARGE and row ACTIVATE activity, reducing memory bandwidth. Branch predictors are also subject to conflict and capacity issues.
Jan
14
comment Two CPUs as a Single System
What about something like MOSIX? While this type of environment does not support a single process using two nodes, it provides some of the advantages of SMP/single system image.
Dec
19
comment Missing L1 cache characteristic
Since you appear to be using only a constant 64B stride, the hardware prefetcher should quickly be trained and accurately prefetch cache blocks.
Dec
17
awarded  Yearling
Nov
16
comment In L1, L2 cache and DRAM, is sequential access faster than random access?
DRAM is not perfectly random access, a read from an open DRAM page/row will be faster than when the bank has no page/row open (since a row ACTIVATE command must be processed by the bank) much less when another page/row is open in the same bank of the DRAM (since that bank needs to process a PRECHARGE command before the row ACTIVATE command can open a new page).
Nov
16
comment Why is loading chunks of data into the cpu cache an efficient way of processing?
My answer to "Why would computers transfer data and instructions from main memory to cache in blocks when this means a single cache miss may overwrite a lot" (a closed question) may sufficiently answer your question.
Nov
16
comment Virtually Indexed Physically Tagged Cache
Since the index bits are taken from the virtual address and must match the physical address (assuming reprobing is not done on a cache miss to detect aliases or page coloring used to avoid them) and the page size is 1 KiB, there will be 10 bits of virtual address that are also physical and 3 of those bits are used for the offset into the 8-byte cache line, so 7 bits can be used to index the cache (so 128 lines with a direct-mapped cache).
Nov
14
comment Byte addressable memory and ISA
Quick pseudo-answer: instruction size is independent of data register size; data buses to main memory are often wider and typically used to fill a cache block at a time (over multiple "beats" [twice bus cycle for DDR]), the connection between L1 cache and the core may be wider than the core's general purpose registers to support load pair/multiple operations or single access FP/SIMD register load/store (when such are larger than the GPRs) and two banks may be accessed simultaneously to support unaligned accesses. (Icache may also provide more than 1 instruction per cycle.)
Nov
12
answered What does the BASE clock speed of an Intel CPU really signify, now that we have Turbo Boost and SpeedStep
Nov
7
comment Why a disk drive could not be connected (physically) to 2+ computers?
+! Linking to Wikipedia's list of shared-disk file systems might be worthwhile.
Nov
1
comment Why does a CPU with lower frequency score better than one with more?
@LưuVĩnhPhúc Again, I agree (I can't say I really like the chosen benchmark, especially with the lack of sub-test results). Single figure of merit is not especially useful (unless the benchmark happens to match the user's targeted workload or at least allow easy fudge factoring based on known traits like mem. bw, LLC size, etc.). However, the OP was asking about results from the specific benchmark. If I wasn't lazy, I would check the SPEC CPU database for results from similar processors. (Sadly, SPEC allows autopar results in base, which makes single-thread results less available.)
Nov
1
comment Why does a CPU with lower frequency score better than one with more?
@LưuVĩnhPhúc I agree. Yet I get the impression that the multithreaded benchmark is more like SPEC Int Rate (each thread runs the same program) which scales relatively well, though the Physics and String Sorting tests (working set 30 MiB and 25 MiB, respectively) might place a higher burden on the memory system. No sub-test values are given, so reasoning about results is difficult. (BTW, in this case 2x cores/threads → 2.07x performance [without turboboost increasing frequency by 40%!}, so obviously there are other factors [cf. 17% faster in single thread].)
Oct
31
comment what does 2 core 4 threads mean in cpu?
@Ramhound You presumably meant 4 instruction streams. Since the i5 is superscalar it can execute multiple instructions in parallel even from a single instruction stream. Simultaneous multithreading allows thread-level parallelism to be converted into instruction-level parallelism, increasing utilization of execution resources.