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Jul
15
comment How can a processor execute more IPS than its frequency?
@PeterCordes There are different voting philosophies. Some claim "useful" is the only criterion, others consider relative merit (for answers). I tend to consider absolute vote count ("nice", "good", "great" post badges imply such should be considered) as well as relative vote count (which helps answer ranking). Surprisingly Meta.SE does not seem to have much on this topic and "How should I vote?" doesn't even have an answer!
Jul
15
comment How can a processor execute more IPS than its frequency?
Self-promotion: How can a CPU deliver more than one instruction per cycle? was asked on the Electrical Engineering Stack Exchange (my answer was accepted and perhaps too highly upvoted).
Jul
6
comment Why aren't there PCIe RAM expansions?
Probably another factor deprecating RAM cards was the move from 32-bit processors to 64-bit processors. More recently, PCIe flash (usually with a DRAM cache) has taken a similar role.
May
22
comment Sharing hardware resources through network: specifically RAM
Note that for some workloads, random access latency is more important than bandwidth (and I suspect your disk bandwidth figure was for large accesses not random 4KiB chunks). Even with networking overheads, transferring 4KiB directly from one system to another would probably be faster than average disk access (with seek, settle, and rotational delays). Before SSDs became popular, there was research on using other systems' RAM for swap space. FuaZe's answer of moving work to the larger system seems more practical.
May
10
comment Content of volatile memory after power loss
It might be worth noting that the interpretation of low charge in the DRAM cell (capacitor) is arbitrary (i.e., low charge could be interpreted as a binary 1). It is not even necessary for every bit cell to be interpreted in the same manner (the memory controller could interpret 32 uncharged bit cells as 0xDEADBEEF). (For Flash one could even argue that the convention of interpreting a freshly erased block as all 1s is less desirable as zero initialization is more common, but I doubt such is a significant consideration.)
Apr
26
comment Why are newer generations of processors faster at the same clock speed?
Improvements in energy efficiency are also a factor given the power wall.
Mar
9
comment How can Windows dump the complete RAM in the hibernation file so fast?
Pages that are not dirty is a more general statement of "paged out to the swap file", this would include executables. (Since executables are somewhat fragmented on disk, this could slow wake-up.) In addition, clean file buffers can presumably just be dropped even if they are not part of a memory mapped file.
Feb
25
comment What are NAF, NAES on RAM?
Since there are parts with NBF, the second letter likely identifies some sequence where less than 26 values are expected to exist. A quick Googling did not find any Kingmax DIMM datasheets (datasheets often provide information on how part numbers are generated), so such information might not be readily available. If you are especially curious, you could contact Kingmax's sales (their contact page gives email addresses).
Feb
17
awarded  Excavator
Feb
17
revised Can a single-threaded program be made to use multiple cores?
capitalized CPU, modest rephrasing
Feb
17
answered Can a single-threaded program be made to use multiple cores?
Feb
17
suggested approved edit on Can a single-threaded program be made to use multiple cores?
Jan
29
awarded  Citizen Patrol
Jan
28
comment Can SMT give worse performance than normal CPU?
Conflict misses are also a problem. DRAM accesses can also have a conflict effect increasing the amount of PRECHARGE and row ACTIVATE activity, reducing memory bandwidth. Branch predictors are also subject to conflict and capacity issues.
Jan
14
comment Two CPUs as a Single System
What about something like MOSIX? While this type of environment does not support a single process using two nodes, it provides some of the advantages of SMP/single system image.
Dec
19
comment Missing L1 cache characteristic
Since you appear to be using only a constant 64B stride, the hardware prefetcher should quickly be trained and accurately prefetch cache blocks.
Dec
17
awarded  Yearling
Nov
16
comment In L1, L2 cache and DRAM, is sequential access faster than random access?
DRAM is not perfectly random access, a read from an open DRAM page/row will be faster than when the bank has no page/row open (since a row ACTIVATE command must be processed by the bank) much less when another page/row is open in the same bank of the DRAM (since that bank needs to process a PRECHARGE command before the row ACTIVATE command can open a new page).
Nov
16
comment Why is loading chunks of data into the cpu cache an efficient way of processing?
My answer to "Why would computers transfer data and instructions from main memory to cache in blocks when this means a single cache miss may overwrite a lot" (a closed question) may sufficiently answer your question.
Nov
16
comment Virtually Indexed Physically Tagged Cache
Since the index bits are taken from the virtual address and must match the physical address (assuming reprobing is not done on a cache miss to detect aliases or page coloring used to avoid them) and the page size is 1 KiB, there will be 10 bits of virtual address that are also physical and 3 of those bits are used for the offset into the 8-byte cache line, so 7 bits can be used to index the cache (so 128 lines with a direct-mapped cache).