111 reputation
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bio website ieee-jbdavid.blogspot.com
location San Jose, CA
age 55
visits member for 4 years, 1 month
seen Sep 25 '12 at 0:42
Mixed Signal Design Verification languages: -Verilog (in all its flavors esp Verilog-AMS) -perl -SKILL (the cadence variant of LISP) -(someday) Python & Matlab