162 reputation
110
bio website None
location Pisa, Italy
age 28
visits member for 3 years, 2 months
seen Jul 6 at 18:33

PhD student in computer science at University of Pisa.


Apr
21
awarded  Notable Question
Feb
5
awarded  Popular Question
Oct
30
awarded  Critic
Jun
29
comment VirtualBox: make host and guest OS talk between each other
Thanks, this solved everything :)
Jun
29
accepted VirtualBox: make host and guest OS talk between each other
Jun
29
asked VirtualBox: make host and guest OS talk between each other
Jun
3
comment What is a processor cache?
@Boris_yo: due to latencies and memory density (you need a lot of silicon to manufacture few hundreds of MB of memory using the structure employed by caches)
Jun
3
comment What is a processor cache?
@Journeyman Geek: feel free to edit my answer ;)
Jun
3
awarded  Commentator
Jun
3
comment How can I make my computer use more RAM?
why on earth he should do something like that?
Jun
3
comment What is a processor cache?
You cannot really answer to such a question in a "comprehensive manner", because this topic is TRULY HUGE.
Jun
3
answered What is a processor cache?
Jun
3
accepted Core 2 duo memory - cache “transfer unit size”
Jun
3
answered Core 2 duo memory - cache “transfer unit size”
Jun
2
comment Core 2 duo memory - cache “transfer unit size”
Of course they may differ, in fact THEY differ - L1 and L2 lines are, in fact, 512 bits wide. But transfer unit between cache hierarchy and bus wideness are two different concepts (wideness tells you how much data you can carry between two levels "at once", while the transfer unit is the amount of data that is exchanged between two levels in response of an event, and usually it is a multiple of the bus wideness), so unfortunately my question still stands :)
Jun
2
awarded  Scholar
Jun
2
accepted Copy only cell content in OOCalc
Jun
2
awarded  Benefactor
Jun
2
comment Core 2 duo memory - cache “transfer unit size”
Thank you for the well-researched answer, but my question was a bit different from what you've interpreted. To put it simply: a L2 line is 64-byte wide. Now, it is well-known that when there is a transfer between two levels of the memory hierarchy (due to prefetching or miss/fault), the amount of data transferred is a multiple of the size of the block of the lower level. So, how many cache lines are transferred in response to a miss? One (so two consecutive transfers from memory, according to the data you postes)? Some more? Anyway, I'm rewarding you the bounty anyway :)
May
29
comment What's the minimum network latency for a 1000 km connection using optic fibers?
@Jader Dias: also take a look at that: en.wikipedia.org/wiki/Snell%27s_law , hope this clears your confusion