I was wondering, when the CPU sends an address on the memory, is it simply selecting which parts of memory get connected to the data bus
Kinda.
A bus is a common wire or set of wires that connects multiple components.
That means anything connected to the bus (the wires that make it) will "hear" anything that anyone else does.
So a typical bus will have address lines (A0-A15, for example), data lines (D0-D7) and then control lines (e.g. RW, READY, etc.)
So the CPU would pull down some address lines to identify an address, some data lines to represent some data, and then for example, pull down RW and maybe some other control line.
It's the responsibility of other devices to listen for that address, and then take action based on the data and control lines. Two devices can respond to signals for the same address--this may be a good or bad thing depending on the system and its electrical characteristcs.
Usually you don't want everything on the bus responding to all addresses so you need things in the middle to direct the signals - like LS chips, a gate array, or other intermediary device.
If this reminds of you of old 10BaseT wired Ethernet where all computers were on 1 physical wire and things like collisions were a thing-you'd be right. So it's necessary that all devices are following a common protocol and don't cause conflicts.
This has limits for speed, that's why technologies have generally moved from the CPU not directly being connected to a bus, and from interconnections generally moving from parallel "bunch of address and data lines" to serial. For example, PCI was a bus, but PCI-E basically operates like an optimized switched Ethernet network. It's also why RAM is more or less directly connected to a memory controller built into the CPU and not on the bus. We are probably not too far from RAM being serial as well.