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In today's x86/x64 motherboards there can be found IOMMU's from Intel and AMD. They allow peripheral devices to perform DMA (direct memory access) operations into system RAM using virtual instead of physical memory addresses.

Now, let's assume that the peripheral device performing the DMA operation using the IOMMU contains some memory to cache system RAM, in order to optimize the processing of frequently accessed data. How can memory coherency be ensured between the peripheral device's cache and the system RAM in this case? Whenever, the peripheral device modifies some data in its cache without writing it back to system RAM, any access to the same memory from the CPU would touch stale data.

The only efficient option I can see is that the peripheral device tells the IOMMU to invalidate each page it reads from system RAM, as this page would be from that moment on cached by the peripheral device. Whenever the CPU would access any page previously read by the peripheral device, a page fault would be triggered. Accordingly, a page fault handler would care for flushing the page out of the peripheral device's cache and reading it back to system RAM.

Is something like this possible at all? Especially, the upcoming HSA programming model makes me believing so, as one of its major features is a unified memory space which is shared between the CPUs and the peripheral compute units. As those compute units most probably will have caches, the memory coherency issue must have been addressed already somehow.

Thank's for you help!
David

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