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I am new in computer architecture but I know the main topics since I had it as a course before. My question is in fact little deep and related to CPU clock cycle and how processor interpret instructions when execution:

Normally, the processor executes instructions at each clock cycle. If one cycle looks like this:

 ----     
|    | 
|    | 
      ----

I want to know how this one cycle single carry the instruction bits. In other word, does CPU interprets this cycle based on raising and falling edges so raising edges represents 1's and falling edges represents 0's?

For example, if an instruction's machine code is 1001 (I know in reality it would be 64 bits or 32 bits based on the processor architecture), so we will have a single like this:

 ----                   ------
|    |                 |
|    |                 |
      ----- ----- -----

Finally, I apologize if my understanding is a bit strange but I really want to visualize the big picture of the "execution journey" inside the CPU.

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I want to know how this one cycle single carry the instruction bits.

The wording of this question is a little hard to understand. Do you mean to ask "how does the CPU receive instructions (1001) with a single clock line"?

It doesn't. A clock signal always look like (4 cycles):

+--+  +--+  +--+  +--+
|  |  |  |  |  |  |  |
+  +--+  +--+  +--+  +--+

It's a metronome. It doesn't carry any information other than timing. It keeps all parts of the CPU working at the same speed. There are lots of connections carrying signals inside a CPU. Signals take time to change (0 -> 1 or 1 -> 0). Some change faster, some slower. Changes take place between rising edges (or falling edges depending on circuit design). The CPU will do the "next step" of the computation at every rising edge (or falling). Eg, fetch, decode, execute, could take 3 cycles. Because the rising (or falling) edges are when signals should have stabilized.

The CPU fetches instructions through other lines, like buses. Typically, the address of the next instruction is placed on the address bus, the instruction is then placed on the data bus, the CPU reads it from the data bus, decodes, executes it. The clock line is for transmitting timing information only, not "data" information.

The 2nd diagram you drew is what 1001 would look like if you were to transmit it serially, but that's a different topic.

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the clock simply triggers the operation on either the rising edge, falling edge or both. IE, the rising edge may set an address on the bus and the falling edge cause the memory to place data from that address onto the bus. To get a better answer, you would have to get the spec sheet for a particular device and see exactly what edges do what. It is all about selecting data (via an address) and moving data around from one address to another. This happens internal to a device like a CPU or GPU or external to to the devices, transferring data from one device to another. Any data transferred via a clock edge is called synchronous. Any data transferred without a clock, as via USB, is called asynchronous. Async data has overhead bits in the data stream to indicate the start and stop of a data byte which is why 9600bps (bits) is not = to 9600Bps (Bytes)

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the cycle just regulates how often a fetch / fetch execute cycle, is done

what you should be looking at is the process whereby you have an instruction in the program counter.. that gets copied to the memory address register, which goes onto the address bus and an instruction comes back and goes into the memory data register aka memory buffer register, and if it requires data at a memory location then that memory address goes into the memory address register and onto the address bus and the data returns on the memory data register.. And The instruction is executed.. The ALU might come into play. Those are the details from what I can recall. If anything is like a "journey" then it's that, it's a process. The cycle just regulates the frequency of the process.. The frequency of the fetch execute cycle.

You need to have a picture of the CPU and RAM and between them the memory bus and data bus. A control bus. That was how I learnt it 15 years ago no doubt from books which were written based on architectures older than those books. But these are the fundamentals that i'm sure are still taught 'cos newer stuff tends to be too complicated for people, and not what teachers tend to be familiar with.

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