In industry it's referred to as electrostatic discharge (ESD) and is far more of a problem now than it has ever been, although it's mitigated somewhat by the fairly recent widespread adoption of policies and procedures that help to lower the likelihood of ESD damaging product.
Regardless, its impact on the electronics industry is larger than many entire industries. It's also a huge topic of study and very complex, so I will just touch on a few points. If you are interested there are numerous free sources, materials and web sites dedicated to the subject. Many people dedicate their careers to this area. Products damaged by ESD have a very real and very large impact on all companies involved in electronics - whether it's as a manufacturer, designer or consumer, and like many things dealt with in industry, its costs are passed along to us.
Per the ESD Association:
“The age of electronics brought with it new problems associated with static electricity and electrostatic discharge. And, as electronic devices became faster and smaller, their sensitivity to ESD increased. Today,
ESD impacts productivity and product reliability in virtually every aspect of today's electronics environment. Industry
experts have estimated average product losses due to static to range [up to] 33%. Others estimate the actual cost of ESD
damage to the electronics industry as running into the billions of dollars annually.”
As devices and their feature sizes (loosely means the smallest component size producible by a given technology) continuously get smaller, they become more susceptible to being damaged by ESD - which makes sense after a little thought. The mechanical strength of the materials used to build electronics in general goes down as their size goes down, as does the materials ability to resist rapid temperature change, referred to usually as thermal mass - just like in 'macro' scale objects. Around 2003 the smallest feature sizes were in the 180 nm range - we are now rapidly approaching 10 nm.
An ESD event that 20 years ago would have been harmless could potentially destroy modern electronics. On transistors the gate material is very frequently the victim, but other current-carrying elements can be vaporized or melted, solder on an IC's pins (technically surface mount equivalent like a ball grid array (BGA) are far more common these days) on a PCB can be melted, and the silicon itself has some critical characteristics (especially its dielectric value) that can be changed by high heat; taken altogether it can change the circuit from a semi-conductor to an always-conductor, which usually ends with a spark and a bad smell when the chip is powered on.
Smaller feature sizes are almost entirely positive from most metrics perspectives - things like operating / clock speeds that can be supported, power consumption, (and tightly coupled) heat generation, etc., but the sensitivity to damage from what would otherwise be considered trivial amounts of energy also goes way up as the feature size goes down.
ESD protection is built into many electronics today, but if you have 500 billion transistors in an integrated circuit, it's not a tractable problem to determine what path a static discharge will take with 100% certainty.
The human body is sometimes modeled (the human-body model; HBM) as having 100 to 250 picofarads of capacitance; in that model the voltage can get as high (depending on the source) as 25 kV (some claim only as high as 3 kV). Using the larger numbers the person would have an energy 'charge' of approximately 150 millijoules. A fully 'charged' person would typically not be aware of it, and it gets discharged in a fraction of second through the first available ground path - frequently an electronic device. Note that these numbers are assuming the person isn't wearing clothing capable of carrying additional charge, which is normally the case.
There are different models for calculating ESD risk and energy levels, and it gets fairly confusing extremely quickly as in some cases they appear to contradict each other. I can't find any source that is more definitive than another, so I'll just link to this excellent discussion of many of the standards and models.
Regardless of the specific method used to calculate it, it isn't and certainly doesn't sound like much energy - but it is more than sufficient to destroy a modern transistor. For context, 1 joule of energy is equivalent - per Wikipedia - to the energy required to lift a medium-size tomato (100 g) 1 meter vertically from the surface of the Earth.
This is on the 'worst' case side of a human-only ESD event, where the human is carrying the charge and discharges it into a susceptible device. A voltage that high from a relatively low amount of charge occurs when the person is extremely poorly grounded. A key factor in what and how much gets damaged isn't actually the charge or the voltage, but the current - which in this context can be thought of how low the resistance of the electronic device's path to ground is.
People working around electronics are typically always grounded, with wrist straps and/or grounding straps on their feet. These are not 'shorts' to ground - the resistance is sized to prevent the workers from being lightning rods (easily getting electrocuted) - wrist bands are typically in the 1 Mohm range, but that still allows the discharge of any accumulated energy quickly. Capacitive and insulative items along with any other charge generating or storing materials are isolated from work areas - things like polystyrene, bubble wrap and plastic cups.
There are literally countless other materials and situations that can result in ESD damage (from both positive and negative relative charge differences) to a device where the human body itself doesn't carry the charge 'internally', it just facilitates it's moving - a cartoon level example would be wearing a wool sweater and socks while walking across a carpet then picking touching a metal object - that creates a significantly higher amount of energy than the body itself could store.
One last point on how little energy it takes to damage modern electronics:
A 10 nm transistor feature size (not common yet, but will be in the next couple of years) has a gate thickness less than 6 nm - which is getting close to what they call a 'monolayer' - a single layer of atoms.
It is a very complicated area, and the amount of damage an ESD event can cause to a device is difficult to predict due to the huge number of variables, including the speed of discharge (how much resistance between the charge and ground), the number of paths to ground through the device, humidity and ambient temperature, and many more. All of these variables can be plugged into various equations that model the impacts, but they are not yet terribly accurate at predicting actual damage, but better at framing the 'possible' damage from an event.
In many cases - and this is very industry-specific (think medical or aerospace), a catastrophic failure inducing ESD event is a far better outcome than an ESD event that passes unnoticed through manufacturing and testing, but instead creates a very minor defect, or perhaps slightly worsens a pre-existing undetected latent defect, which in both scenarios can get worse over time due to either additional 'minor' ESD events or just regular usage, ultimately resulting in a catastrophic and premature failure of the device (aka infant mortality) in an artificially shortened time frame not predicted by reliability models (which are the basis for maintenance / replacement schedules). Because of this danger, and it's easy to think of terrible situations - a pacemakers microprocessor, or flight control instruments - coming up with ways to test for and model latent ESD induced defects is a major research area right now.
Now from a consumer who doesn't work in or know much about electronics manufacturing it may seem to not be an issue - by the time most electronics are packaged for sale, there are numerous safeguards in place that would prevent most ESD damage - the sensitive components are physically inaccessible and more 'convenient' paths to ground are available, (e.g. a computer chassis is tied to ground - discharging ESD into it will almost certainly not damage the CPU inside the case, but instead take the low resistance path to ground via the power supply and wall power) or alternatively no reasonable current carrying paths are possible - many cell phones have non-conductive exteriors and only have a ground path when being charged.
For the record, I have to take ESD training every three months, so I could just keep going. But I think this should be sufficient to answer your question. I believe everything in this to be accurate, but I would strongly advise reading up on it directly to get better acquainted with the phenomena if I haven't destroyed your curiosity for good.
One thing that people find counterintuitive is that the bags that you frequently see electronics stored and shipped in - anti-static bags - are also conductive. Anti-static means that the material will not collect any meaningful charge from interacting with other materials, but in the ESD world it's equally important that, to the extent possible, everything has the same 'ground' voltage reference, so work surfaces (ESD mats), the ESD bags and other materials are all typically kept tied to a common ground (either by simply not having an insulative material between them) or more explicitly by wiring low resistance paths to ground between all work benches, the connectors for the workers wrist bands, the floor, and some equipment. There are safety issues here - if you work around high explosives and electronics, your wrist band might be tied directly to ground rather than with a 1 Mohm resistor. If you work around very high voltage, you would not ground yourself at all.
Another quote on the costs of ESD from Cisco - which might be even be a bit conservative, as the collateral damage from field failures for Cisco typically does not result in the loss of life, which can raise that 100x referred to by orders of magnitude:
It is amazing when you look at the cost associated with ESD-damaged components. The costs related to the failure depends on when the damage was discovered. It is estimated that if the damage is found:
- During assembly the cost is 1 times the cost of assembly and labor.
- During test the cost is 10 times the cost of assembly and labor.
- At the customer site the cost is 100 times the cost of assembly and labor