00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller (rev 06) Subsystem: CLEVO/KAPOK Computer Device 5455 00:02.0 VGA compatible controller: Intel Corporation 4th Gen Core Processor Integrated Graphics Controller (rev 06) Subsystem: CLEVO/KAPOK Computer Device 5455 Kernel driver in use: i915
You can see the memory controller is shown as pci device 00:00.0 being attached on the 00:00.0 bus. I guess a driver for this device isn't shown because just like PCI itself it is such a standard that the way the kernel uses it is hard-wired into the code. (No driver needed because alternative I/O writing methods to the devices registers basically don't exist.)
And reading on wikipedia:
In modern systems the performance difference between the CPU and main memory has grown so great that increasing amounts of high-speed memory is built directly into the CPU, known as a cache. In such systems, CPUs communicate using high-performance buses that operate at speeds much greater than memory, and communicate with memory using protocols similar to those used solely for peripherals in the past. These system buses are also used to communicate with most (or all) other peripherals, through adaptors, which in turn talk to other peripherals and controllers. Such systems are architecturally more similar to multicomputers, communicating over a bus rather than a network. In these cases, expansion buses are entirely separate and no longer share any architecture with their host CPU (and may in fact support many different CPUs, as is the case with PCI). What would have formerly been a system bus is now often known as a front-side bus.
I don't like to use the southbridge/northbridge concept for describing I/O because its more form a physical, hardware point of view. I see I/O as buses, being connected to devices. Which can be controllers that form bridges to other buses.
On a modern computer system, the bus connecting the CPU to everything else is now named front side bus. I/O from the CPU to the world now works over a front-side bus connection instead of the old system bus. (which consisted of the address, data and control bus. (that get used to explain the memory, cpu concept))
All of this is pretty much nothing official, because I only have wikipedia and my computer for learning, So I'd like to ask some experts.
Is all of this correct? Is this true? Because:
That would mean main memory is actually attached and mapped as I/O or not? The CPU cache is the actual memory that uses this easy systembus (address data control bus) concept. And when we talk about the simplest form of physical addressing what do we mean? (0x0FFF, 010FFh) Memory locations of course. But that's not the case, since at least the 90`s when the Front-side bus concept was introduced.