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After viewing lspci -k:

00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v3/4th Gen Core Processor DRAM Controller (rev 06)
    Subsystem: CLEVO/KAPOK Computer Device 5455
00:02.0 VGA compatible controller: Intel Corporation 4th Gen Core Processor Integrated Graphics Controller (rev 06)
    Subsystem: CLEVO/KAPOK Computer Device 5455
    Kernel driver in use: i915

You can see the memory controller is shown as pci device 00:00.0 being attached on the 00:00.0 bus. I guess a driver for this device isn't shown because just like PCI itself it is such a standard that the way the kernel uses it is hard-wired into the code. (No driver needed because alternative I/O writing methods to the devices registers basically don't exist.)

And reading on wikipedia:

In modern systems the performance difference between the CPU and main memory has grown so great that increasing amounts of high-speed memory is built directly into the CPU, known as a cache. In such systems, CPUs communicate using high-performance buses that operate at speeds much greater than memory, and communicate with memory using protocols similar to those used solely for peripherals in the past. These system buses are also used to communicate with most (or all) other peripherals, through adaptors, which in turn talk to other peripherals and controllers. Such systems are architecturally more similar to multicomputers, communicating over a bus rather than a network. In these cases, expansion buses are entirely separate and no longer share any architecture with their host CPU (and may in fact support many different CPUs, as is the case with PCI). What would have formerly been a system bus is now often known as a front-side bus.

I don't like to use the southbridge/northbridge concept for describing I/O because its more form a physical, hardware point of view. I see I/O as buses, being connected to devices. Which can be controllers that form bridges to other buses.

On a modern computer system, the bus connecting the CPU to everything else is now named front side bus. I/O from the CPU to the world now works over a front-side bus connection instead of the old system bus. (which consisted of the address, data and control bus. (that get used to explain the memory, cpu concept))

CPU Dual

All of this is pretty much nothing official, because I only have wikipedia and my computer for learning, So I'd like to ask some experts.

Is all of this correct? Is this true? Because:

That would mean main memory is actually attached and mapped as I/O or not? The CPU cache is the actual memory that uses this easy systembus (address data control bus) concept. And when we talk about the simplest form of physical addressing what do we mean? (0x0FFF, 010FFh) Memory locations of course. But that's not the case, since at least the 90`s when the Front-side bus concept was introduced.

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  • I'm not sure which physical bus is used as you'd also have to consider DMA (Direct Memory Access) which allows other system components to access the RAM without utilizing the CPU. But in regards to your addressing question ... each process has a linear memory space in which it can't differentiate which part of it is in which physical memory part. You'd have to look into paging and the inner working of an MMU to get a better understanding on how that mapping is achieved but your psychical memory is usually abstracted by the OS. – Seth Oct 28 '16 at 11:28
  • The FSB is a thing of the past. It’s even in the Wikipedia article, in the third paragraph. Also, this is more of a Computer Science question. – Daniel B Oct 28 '16 at 11:34
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    "And when we talk about the simplest form of physical addressing what do we mean?" That's why I mentioned 'physical' I meant addressing on a system software level(the level the kernel runs on) all of that is besides paging and this concept would be, considering the dimension my question is asked in, a high level technology. – Junaga Oct 28 '16 at 11:35
  • It actually would play right into that as even in your kernel you could have components that directly interact with your paging process and some which are already using an abstraction of that. See also: Linux Page Table Management and MMU If you want to do this on a really low level look at assembler code or am I misunderstanding you? – Seth Oct 28 '16 at 11:43
  • @DanielB it only appears to be obsolete/out of date, because from a physical point of view the front-side bus connects the CPU to I/O (that is the DRAM controller always which is also a processor and responsible for DMA) that is called northbridge(this is a name form a hardware point of view) with the new Intel 5 Series this component is actually build into the CPU itself, en.wikipedia.org/wiki/Intel_5_Series#Design_concept look at the images on the right. But it still is the front side bus which connects the cache used by different cores to the DRAM controller. – Junaga Oct 28 '16 at 11:44
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Modern Intel's CPUs use more sophisticated internal interconnect technology called "Coherent Fabric", in various incarnations. The reports from software tools are simply misleading because the logical architecture of configuration and resource allocation spaces for peripheral devices still remains in classic PCI format, for convenience and software PNP compatibility. So the logical protocols remain the same, but physically the data are moved much, much faster.

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Most of your question contains concepts that are

  • Outdated (Intel has been releasing platforms and CPUs where these things are not true since at least 2011)
  • Incorrect (Main memory access is not a form of general purpose I/O and does not use the Front Side Bus or any other type of general purpose I/O bus; it always uses a dedicated memory bus).

Even this fairly outdated picture depicts the memory using a separate, dedicated memory bus separate from PCI/FSB:

old system architecture


To get a sense of how modern Intel platforms work, you should read up on the following:

Note that as of the introduction of the Platform Controller Hub, there is no more distinction between the northbridge and southbridge; they're integrated into a single chip (which, on low-power systems, is further integrated into the CPU package!)


The lspci output is deceiving, and is an artifact of the way the Linux kernel is designed in software. You're not actually doing memory accesses over PCI. In general, it is a bad idea to rely on the architecture of an operating system to inform your knowledge of system hardware, because subsystems and abstractions in operating systems are often re-purposed to "similar" use cases even if the underlying hardware does things in a completely different way.


Further proof that even the modern PCH based architecture does not access main memory over the I/O bus:

modern architecture

I'm still not sure this is a good question to be asking though, because you're basically making a bunch of false assumptions and relying on very old information to make inferences that are partially or mostly false. So the only real answer that makes sense here is "No."

  • >"Incorrect (Main memory access is not a form of general purpose I/O and does not use the Front Side Bus or any other type of general purpose I/O bus; it always uses a dedicated memory bus)." >"does not use the Front Side Bus." Of course memory is connected to the cpu over the front side bus? not directly of course the memory controller is in between, but just look at your own graphic, the memory bus just connects the mm with the northbridge aka DRAM controller and it doesn't matter what chipset we are talking about even with todays system the northbridge is just build into the CPU. – Junaga Oct 28 '16 at 13:08
  • @Junaga, hey, a man told you that your concepts are outdated. The concept of "Northbridge" was when everything else was connected to Pentium CPU via a "hublibk interface", which was a pretty fast parallel-serial proprietary bus. However, not fast enough. Internally, modern INTEL CPUs do not use any busses, they use switch fabric. And the DDRx controller is connected directly to the fabric. wccftech.com/intel-cannonlake-cpus-8-cores However, logically everything still uses all configuration aspects of PCI devices. – Ale..chenski Oct 31 '16 at 15:52

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