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I'm assuming of course NAND SSDs with ECC are correcting the data by using a voting system i.e. if both bit holders's bits match. Nasa used like 5 on the first ship. So then how could SSDs corrupt your important data by fly writes and all these problems the young technology faces when it has ECC!?

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2 Answers 2

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I'm assuming of course NAND SSDs with ECC are correcting the data by using a voting system

Uhm, no. ECC usually does not work by comparing multiple copies. Instead it only needs 10 bits of stored data to detect and correct a 1 bit fault.

A simplied way of how that works is show here.

So then how could SSDs corrupt your important data by fly writes and all these problems the young technology faces when it has ECC?

Because data stored on the NAND chips is not the only place where it can be corrupted.

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  • where else has it been known to get corrupted? Nov 25, 2016 at 10:51
  • Easiest example I can think of is in one the the CPUs on the SSD. (SSD controllers often are single to triple core ARM CPU's and some memory. The latter may or may not be ECC).
    – Hennes
    Nov 25, 2016 at 11:06
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    "Instead it only needs 10 bits of stored data to detect and correct a 1 bit fault." -- Apparently you're describing the Hamming code (?) used in DRAM modules, and omitting the salient attribute of 8-bits of data (in the 10 bits). There are many types of ECC, and the ECC used for DRAM (8 bits of data) is not like NAND flash ECC (which protects a block/sector). FYI the ECC used in HDDs used a Fire code of 56 bits for the 512-bytes of data, can detect & correct an error burst up to 11 bits, and detect (but not correct) a longer burst of errors.
    – sawdust
    Nov 28, 2016 at 4:56
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I'm assuming of course NAND SSDs with ECC are correcting the data by using a voting system i.e. if both bit holders's bits match.

You assume incorrectly how ECC works.

The ECC capability required by NAND varies by chip.
The NAND chip manufacturer will specify a minimum number of bits that must be correctable (by the host) per block. Fewer bits could indicate more reliable NAND.
(Blocks that are tested to have more than this number of defective bits would be flagged as "bad blocks" by the manufactuter.)

The NAND installed on SBCs typically require correction capability of 1, 2, or 4 bits per ~512 bytes. Chips in SSDs could (?) require more bits.
The length of the ECC depends on the code implementation; for example it can be 7 bytes for correctability of 4 bits by a NAND controller that uses BCH code.

The Linux kernel can report this NAND attribute during boot:

[    0.780000] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xf1
[    0.780000] nand: Micron MT29F1G08ABAEAWP
[    0.790000] nand: 128 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
[    0.790000] atmel_nand 80000000.nand: minimum ECC: 4 bits in 512 bytes
[    0.800000] atmel_nand 80000000.nand: Initialize PMECC params, cap: 4, sector: 512

The ECC data is generated prior to the writimg of the block of data by the code's (e.g. Hamming, BCH, or Fire) algorithm (which evaluates a polynomial).
On a read, an inverse algorithm is fed the data and ECC bytes to produce a verdict of good read, correctable read, or uncorrectable read.
The algorithms can be implemented in hardware or software.

So then how could SSDs corrupt your important data by fly writes and all these problems the young technology faces when it has ECC!?

You seem to imply that somehow ECC should prevent or inhibit data "corruption".
ECC has no such capability; the purpose of ECC is to detect errors when reading, and possibly correct those errors (within certain limits) after data loss has occured.

Data loss in NAND flash has been attributed to power loss, memory wear, Read disturb, and X-ray effects.

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