What does "32GB(8Gbx4DR)" mean in the dumped RAM info?

I dumped my RAM DIMM info. It contains string like `32GB(8Gbx4DR)`. I know its capacity is 32GB. What does `8Gbx4DR` mean?

And I heard about the concepts like `rank`, `channel`, `bank`. I understand that:

• A rank refers to the chips that make up the bit width requirement of the memory controller's channel width.

• A rank is made of banks.

But how can I map the dumped info to these concepts?

Below is the screenshot of the dumped info:

• This is a server board.
• Each CPU has 2 memory controllers.
• Each memory controller has 3 channels.
• Each channel can support 2 slots of DIMM.

Some reference pages and documents I reviewed regarding RAM setups:

And back to my `32GB(8Gbx4DR)` question. Now I believe I can figure it out:

• 1 DRAM chip = 8Gb (lower b) (According to the spec)
• DDR* requires 64-bit channel width. and `x4` means a single DRAM chip provides 4-bit width. So 16 DRAM chips are required per RANK to meet the channel width.
• `DR` means 2/dual ranks per DIMM

So the total size of a DIMM = 2 * 16 * 8Gb = 32GB (upper B)

And if include the ECC (Error Correcting Code), there needs more DRAM chips. For a single byte, a single ECC bit is needed.

For example, with 8Gb x4 DRAM chip, the calculation for a 16GB dual-rank DIMM with ECC is like this. (The important thing is to calculate based on bits.)

The DDR* requires 64-bit width for a rank to serve a channel. And x4 means a single DRAM chip has 4-bit width. So a rank will comprise 64/4 = 16 chips.

With dual ranks, we need `32` DRAM chips.

To achieve a total DIMM capacity of 16GB, the size of each DRAM chips should be 16GB /32 = 16*8 Gb /32 = 4 Gb.

Each 8 bits need a ECC bit, so 16GB needs: 16*8 Gb /8 = 16Gb. ECC can be implemented with DRAM chips as well. And 16Gb is just `4` pieces of 4-Gb DRAM chips.

So in total, we need `32 + 4 = 36` 4Gbx4 DRAM chips.

• And you're sure it's DR as you say and not DDR? What program dumped that info? can you paste it and name the program? Commented May 18, 2017 at 7:54
• @barlop Yes, definitely sure. Unless the tool I am using has some bug. Commented May 18, 2017 at 7:54
• Normally a program would say like how many ram modules you have, like 2*16GB or 2x16GB would be 2 modules each. Maybe you have 8GBx4 then the question would be what the DR stands for and it wouldn't be DDR 'cos that'd be about the ram modules. Commented May 18, 2017 at 7:57
• what is the name of the program, the tool? Commented May 18, 2017 at 7:58
• I hadn't heard of the intel customer script before but I see it exists. Though I can't even find any screenshot on google images of anybody else that has used the intel customer script to give that info screen.. Hopefully you will get an answer here but also it's worth trying the intel forum communities.intel.com/community/tech specifically communities.intel.com/community/tech/servers Commented May 18, 2017 at 8:06

That's Correct. This specific naming convention is as follows(each vendor differs slightly):

[32GB][8Gb][x4][DR]

[DIMM_TOTAL_SIZE(in gigabytes)] [DRAM SIZE(in gigabits)] [number of data bits per dram (column width)] [number of ranks]

32GB = (8 * 16 * 2) / 8

8 gigabits * 16 chips (drams) per rank * 2 ranks = 256 gigabits

256 gigabits / 8 = 32 gigabytes.

The number of bank resource a DRAM contains (density) is internal to the DRAM and not consequential here. It is factored into [DRAM SIZE(in gigabits)].

For different DRAM width of the same density:

a x4 will contain twice the number of bank resources of that of a x8

a x8 will contain twice the number of bank resources of that of a x16

there is a performance advantage to having more bank resources per dram, since a dram can only have one page (or row) open per bank at any given time. In general, a x4 will perform better than a x8, which will perform better than a x16 (all other factors being equal) due to pipelining of transactions performed by the memory controller. This is because it takes time (latency) to open a page (activate) and close a page (precharge). You can effectively double the number of bank resources on a channel by adding a rank, but this is less beneficial than doubling the bank resource of the dram due to the fact that only one rank can communicate on the bus at any given time.

-Paul K

The x4DR fits within the techspecs and probably Points to the dualrank "feature" of this particular RAM:

• Thanks. Now I know that `x4` means the bit width of each DRAM chip. DDR* memory has a bit width of 64 bits. So each rank requires 16 DRAM chips. `DR` means `dual rank` so the DIMM has 2 ranks, which means there're 32 DRAM chips on this DIMM. So, one last thing, what does the `8Gb` mean? Why the `b` is lower case? Commented May 18, 2017 at 8:30
• @smwikipedia RAM chip sizes are given in bit, hence the small 'b'. They’re 8 Gigabit chips. Specs of the chip in question. Commented May 18, 2017 at 8:45
• Specs of the DIMM in question show that it's a registered chip that has 36 of those 8Gigabit chips, for error correction. Commented May 18, 2017 at 8:54
• @smwikipedia Daniel's link is about the individual chips, my link is about the DIMM (which contains several of those chips). Commented May 29, 2017 at 10:47
• @smwikipedia Read the DIMM spec, search for K4A8G085WB in the Data Sheet. It's listed right there. Commented May 29, 2017 at 10:52