Let's assume I have a 32 bits addressable memory and a 4 kib direct-mapped cache. Let's say that every entry (line) of the cache is composed of a unique word (32 bits).
We can infer that the index's size is 10 bits, since 4*2^10 bytes / 4 = 2^10 words = 2^10 lines.
Now, since there is only one word per line, I assume we don't need an offset field. Therefore, the cache's addresses are decomposed this way:
- Bits 0 to 9 : Index
- Bits 10 to 31: Label
Is my logic wrong somehow ?