Let's assume I have a 32 bits addressable memory and a 4 kib direct-mapped cache. Let's say that every entry (line) of the cache is composed of a unique word (32 bits).

We can infer that the index's size is 10 bits, since 4*2^10 bytes / 4 = 2^10 words = 2^10 lines.

Now, since there is only one word per line, I assume we don't need an offset field. Therefore, the cache's addresses are decomposed this way:

  • Bits 0 to 9 : Index
  • Bits 10 to 31: Label

Is my logic wrong somehow ?

  • For the people who are downvoting, can I have a reason ? Maybe an advice to improve my question ? – Arthur Deschamps May 28 '17 at 20:12

We need 2 bits for the offset, because a 32 bits value has 4 bytes and each byte might be accessed individually, and thus the offset might be of 0,1,2 or 3.

Therefore, an address is decomposed this way by the direct-mapped cache:

  • Bits 0 to 1: offset
  • Bits 2 to 11: index
  • Bits 12 to 31: label

A cache line is typically 64 bytes, the offset bits 0-6 select a byte on the line.

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